Toshiba T1200 User Manual page 179

C.4 PIH DBSCRIPl'Iml
TABLE C-l Pin Description
Pin
1/0
SYMBOL
Signal name and Description
1,2
I AD11
AD111-A121:
-A12
Two of the lower 16 bits of the data bus from the
CPU, and are bidirectional
3 Vcc +
5Vdc
4 GND
Ground
5- I AD13 AD131-AD151 :
7 -15 Three of the lower 16 bits of the data bus from the
CPU. They are all bidirectional.
8-
I AD16 AD161-AD191 :
11 -19 Upper 4bits of the address bus from the CPU
12 I RESET RESETO: Power on reset signal
13
I
lOW 10WRO: 110 write command signal
14 I lOR 10RDO: 110 read command signal
15 GND Ground
16
0
INTCS INTCSO: Interrupt controller chip select signal
17 I
BOLEN BDLENO:
EVEN data enable signal
When WDLEN is "0", it is inhibited.
18
0
A19-16
A191-161:
-
Upper 4 bits of the address bus, and during the DMA
21
cycle, they become in the state of high impedance
22
0
A15-13 A151-131:
-
Three of the lower 16 bits of the address bus, and
24 during the DMA cycle;
10071-01 ~A151-081
DMAD71-01 ~A071-001
25 I
AOB AOB1:
Bit "0" of the system address.
C - 4