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Pin I/O
SYMBOL
Signal name and Description
72
I
AEN
OMAEN
OMA address enable signal. This signal is generated
from the AEN signal of the 82C37
73
0
CPCLK
CPClK1
CPU Clock: 4.77 MHz (Slow)
9.54 MHz (Fast)
74
0
XMEMR
XMEROO
Memory read command
75
110
MEMW
MEWRO
Memory write command
76
I
ROY
IOROY1
110 ready signal
77
0
DMSL
OMSELO
V-RAM select signal
78
Vcc
+
5V
79
0
ECRT
FLTOSl1
Flat display select signal
80
0
OFNT
CHFONTO
Double font select signal
81
0
lOOMS
10OMSO
100 Bus memory select signal
82
I
MeReS
MeReso
Machine control register chip select
83
0
BWHEN
BWHENO
High data (odd) enable signal for byte to the
1/0
bus
84
0
BWOIR
BWOIR1
Specifies data direction. Held to be low except 10WR
and MEMWtothe
1/0
bus.
85
I
AOO
A001
Address line bit 0
A - 8
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