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UAOO-UAOS, UA14 (AOOl-AOSl,A14l) : CPU Address (Input)
These are address data line from the CPU or OMAC, and when
it is at high level, it shows logic true.
U~OO-UA03
(AO-A3) are used for selecting one of the I/O
ports included in the gate array during read or write
operation to the I/O port of the gate array.
When memory
read or write operation to the V-RAM is performed, memory
location is selected by the address lines UAOO-UAOS (AO-AS)
and also by those of A06-A13 which are supplied directly to
the V-RAM without passing the gate array.
BOOO-B007 (SOOl-S07l)
: a-bit Data Bus (Input/Output)
Tne~e
ClLe
O-Ul.l.
UCll.Cl
.L.l.llt::b
allu
WUt::1I
'-uuo<::
O ...
' : f " Q ... .,.
Q ...
<::
Q
...
h~nh
l~u~l
_
i~
~hnw~
lnni~
~ru~.
These lines are used for
input or output or tne aata aur1ng reaa
or wrl.t:.e operat:.l.ulI
to the I/O port inside the gate array or to the V-RAM.
IOROYI : I/O Ready (Output)
When access requirement to the V-RAM is generated from the
CPU or OMAC, if OMESLO becomes low, the gate array keeps
this signal at low level, and puts the CPU and OMAC in the
waiting position until the access is enabled.
RSTO (RESETO) : (Reset)
When this signal is at low, the gate array is reset.
0.S.2 V-RAM signals (34 lines)
UROO-UR04 : CPU/Refresh Address 00-04 (Input)
RAOS-RA12 : Refresh Address OS-12 (Input)
These are address lines for the V-RAM.
The S address signals UROO-UR04 are directly connected to
the address input pin of the V-RAM, while the upper a
signals on the address lines RAOS-RA12 are multiplexed with
the address signals A06l-A13l of the I/O bus and are
connected to the address input pin of the V-RAM.
There are two modes in the accessing the V-RAM, one is the
mode in which memory read or write operation from the CPU is
executed through the I/O bus, and the other is the one in
which the direct display fresh (read only) is performed from
the gate array.
D - 11
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