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Pin
1/0
SYMBOL
Signal name and Description
14
I
DACKO
DACKOO
DMA acknowledge signal for channel 0
15
GND
Ground
16
110
lOR
10RDO
1/0 bus data read command
17
110
lOW
10WRO
1/0 bus data write command
18
0
RESET
RESETO
Reset active low output
19
I
BHE
BHEO
Bus high enable
20
I
S20
CPU status signal bit 2
21
I
S10
CPU status signal bit 1
22
I
SOO
CPU status signal bit 0
23
1/0
CRGO
CRGOO
This gate sends a low pulse to
RQ/GT
pin of the CPU
when the GA receives a HRQDM 1 signal from the
82C37. Then it sends a HOLDA 1 signal to the 82C37
when it receives a low pulse to the CPU from this gate
when the DMA cycle is completed.
24
0
ROMCS
ROMCSO
ROM select signal (ROM
=
FOOOO - FFFFF)
25
1/0
BAMCS
BAMCSO
Back up memory chip select
26
1/0
AOBB
AOBB1
Address 0 for byte bus (Buffer)
27
1/0
XIOR
XIORDO
1/0 read command (Buffer)
A - 4
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