Intel 87C196CA Supplement To User’s Manual page 6

8XC196L X SUPPLEMENT
Figure
2-1 8XC196L x Block Diagram ............................................................................................2-2
2-2 Clock Circuitry (87C196LA, LB Only) ...........................................................................2-3
2-3 Internal Clock Phases (Assumes PLL is Bypassed).....................................................2-4
2-4 Effect of Clock Mode on Internal CLKOUT Frequency.................................................2-5
2-5 Unerasable PROM 1 (USFR1) Register (LA, LB Only) ................................................2-6
3-1 Register File Address Map ...........................................................................................3-3
4-1 Interrupt Mask (INT_MASK) Register...........................................................................4-3
4-2 Interrupt Mask 1 (INT_MASK1) Register......................................................................4-4
4-3 Interrupt Pending (INT_PEND) Register ......................................................................4-5
4-4 Interrupt Pending 1 (INT_PEND1) Register .................................................................4-6
4-5 PTS Select (PTSSEL) Register ....................................................................................4-7
4-6 PTS Service (PTSSRV) Register .................................................................................4-8
5-1 Ports 1, 2, 5, and 6 Internal Structure (87C196LA, LB Only) .......................................5-3
5-2 Ports 3 and 4 Internal Structure (87C196LA, LB Only) ................................................5-6
6-1 SSIO 0 Clock (SSIO0_CLK) Register...........................................................................6-1
6-2 SSIO 1 Clock (SSIO1_CLK) Register...........................................................................6-2
7-1 EPA Block Diagram (87C196LA, LB Only)...................................................................7-2
7-2 EPA Block Diagram (83C196LD Only) .........................................................................7-3
7-3 EPA Interrupt Mask (EPA_MASK) Register .................................................................7-4
7-4 EPA Interrupt Mask 1 (EPA_MASK1) Register ............................................................7-4
7-5 EPA Interrupt Pending (EPA_PEND) Register.............................................................7-5
7-6 EPA Interrupt Pending 1 (EPA_PEND1) Register........................................................7-5
7-7 EPA Interrupt Priority Vector Register (EPAIPV)..........................................................7-6
8-1 Integrated J1850 Communications Protocol Solution...................................................8-1
8-2 J1850 Communications Controller Block Diagram .......................................................8-2
8-3 Huntzicker Symbol Definition for J1850........................................................................8-7
8-4 Typical VPW Waveform................................................................................................8-7
8-5 Bit Arbitration Example .................................................................................................8-8
8-6 J1850 Message Frames ...............................................................................................8-9
8-7 Huntzicker Symbol Definition for the Normalization Bit ..............................................8-10
8-8 Definition for Start and End of Frame Symbols ..........................................................8-11
8-9 IFR Type 1 Message Frame.......................................................................................8-12
8-10 IFR Type 2 Message Frame.......................................................................................8-13
8-11 IFR Type 3 Message Frame.......................................................................................8-13
8-13 J1850 Transmit Message Structure............................................................................8-14
8-12 J1850 Transmitter (J_TX) Register ............................................................................8-14
8-15 J1850 Receive Message Structure.............................................................................8-15
8-14 J1850 Receiver (J_RX) Register ................................................................................8-15
8-16 J1850 Command (J_CMD) Register ..........................................................................8-17
8-17 J1850 Configuration (J_CFG) Register ......................................................................8-18
8-18 J1850 Delay (J_DLY) Register ...................................................................................8-20
8-19 J1850 Status (J_STAT) Register................................................................................8-21
9-1 Reset Source (RSTSRC) Register ...............................................................................9-1
10-1 Clock Circuitry (87C196LA, LB Only) .........................................................................10-2
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FIGURES
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