Ssio 0 Clock Register; Ssio 0 Clock (Ssio0_Clk) Register - Intel 87C196CA Supplement To User’s Manual

The synchronous serial I/O (SSIO) port on the 8XC196Lx has been enhanced, implementing two
new special function registers (SSIO0_CLK and SSIO1_CLK) that allow you to select the oper-
ating mode and configure the phase and polarity of the serial clock signals.
6.1

SSIO 0 CLOCK REGISTER

The SSIO 0 clock (SSIO_CLK) register selects the phase and polarity for the SC0 clock signal.
In standard mode, SC0 is channel 0's clock signal. In duplex and channel-select modes, SC0 is
the common clock signal for both SSIO channels.
SSIO0_CLK
The SSIO 0 clock (SSIO0_CLK) register configures the serial clock for channel 0. In standard mode,
the SC0 is channel 0's clock signal. In duplex and channel-select modes, SC0 is the common clock
signal for both SSIO channels.
7
— —
Bit Bit
Number Mnemonic
7:2 —
1 PHAS
0 POLS
SYNCHRONOUS SERIAL I/O PORT
— —
Reserved; for compatibility with future devices, write zeros to these bits.
Phase and Polarity Select
For normal transfers, these bits determine the idle state of the serial
clock and select the serial clock signal edge on which the SSIO samples
incoming data bits or shifts out outgoing data bits. These bits are ignored
for handshaking transfers. Use SSIO0_ CON to select the type of data
transfer (normal or handshaking) for channel 0.
For transmissions
PHAS POLS
0 0
0 1
1 0
1 1
For receptions
PHAS POLS
0 0
0 1
1 0
1 1
Figure 6-1. SSIO 0 Clock (SSIO0_CLK) Register
— —
Function
low idle state; shift on falling edges
high idle state; shift on rising edges
low idle state; shift on rising edges
high idle state; shift on falling edges
low idle state; sample on rising edges
high idle state; sample on falling edges
low idle state; sample on falling edges
high idle state; sample on rising edges
CHAPTER 6
Address: 1FB5H
Reset State:
00H
0
PHAS POLS
6-1