Epa Mask Registers; Epa Interrupt Mask (Epa_Mask) Register; Epa Interrupt Mask 1 (Epa_Mask1) Register - Intel 87C196CA Supplement To User’s Manual

8XC196L X SUPPLEMENT
7.1.1

EPA Mask Registers

Figures 7-3 and 7-4 illustrate the EPA mask registers, EPA_MASK and EPA_MASK1, for the
8XC196Lx microcontroller family.
EPA_MASK
The EPA interrupt mask (EPA_MASK) register enables or disables (masks) interrupts associated with
the shared EPA x interrupt.
15
Lx —
7
0VR2
Bit
Number
†
Setting a bit enables the corresponding interrupt as a EPA x interrupt source. The shared
15:0
EPA x interrupt is enabled by setting its interrupt enable bit in the interrupt mask register
(INT_MASK.0 = 1).
†
Bits 2–5 and 14–15 are reserved on the 8XC196L x device family. For compatibility with future
devices, write zeros to these bits.
Figure 7-3. EPA Interrupt Mask (EPA_MASK) Register
EPA_MASK1
The EPA interrupt mask 1 (EPA_MASK1) register enables or disables (masks) interrupts associated
with the multiplexed EPA x interrupt.
7
— —
Bit
Number
7:4 Reserved; for compatibility with future devices, write zeros to these bits.
†
3:0 Setting a bit enables the corresponding interrupt as a multiplexed EPA x interrupt source.
The multiplexed EPA x interrupt is enabled by setting its interrupt enable bit in the
interrupt mask register (INT_MASK.0 = 1).
†
87C196LA, LB only; reserved on 83C196LD.
Figure 7-4. EPA Interrupt Mask 1 (EPA_MASK1) Register
7-4
— EPA6 EPA7
OVR3 — —
Function
— — COMP0
Function
Address:
Reset State:
EPA8 EPA9 OVR0
— — OVR8
Address:
Reset State:
† †
COMP1 OVRTM1
1FA0H
0000H
8
OVR1
0
OVR9
1FA4H
00H
0
OVRTM2