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8XC196L X SUPPLEMENT
PTSSRV
The PTS service (PTSSRV) register is used by the hardware to indicate that the final PTS interrupt has
been serviced by the PTS routine. When PTSCOUNT reaches zero, hardware clears the corresponding
PTSSEL bit and sets the PTSSRV bit, which requests the end-of-PTS interrupt. When the end-of-PTS
interrupt is called, hardware clears the PTSSRV bit. The end-of-PTS interrupt service routine must set
the PTSSEL bit to re-enable the PTS channel.
15
LA
—
7
—
15
LB
—
7
J1850RX
15
LD
—
7
—
Bits
†
14:0
A bit is set by hardware to request an end-of-PTS interrupt for the corresponding interrupt
through its standard interrupt vector.
The standard interrupt vector locations are as follows:
Bit Mnemonic Interrupt
EXTINT
Reserved
RI
TI
SSIO1
SSIO0
J1850ST (LB)
J1850RX (LB)
J1850TX (LB)
AD (LA, LB)
EPA0
EPA1
EPA2
EPA3
††
EPA x
††
PTS service is not useful for shared interrupts because the PTS cannot readily
determine the source of these interrupts.
†
Bit 13 is reserved on the 8XC196L x devices and bits 6–8 are reserved on the 87C196LA and
83C196LD. For compatibility with future devices, write zeros to these bits.
4-8
EXTINT
—
—
AD
EPA0
EXTINT
—
J1850TX
AD
EPA0
EXTINT
—
—
—
EPA0
EXTINT pin
†
—
SIO Receive
SIO Transmit
SSIO 1 Transfer
SSIO 0 Transfer
J1850 Status
J1850 Receive
J1850 Transmit
A/D Conversion Complete
EPA Capture/Compare Channel 0
EPA Capture/Compare Channel 1
EPA Capture/Compare Channel 2
EPA Capture/Compare Channel 3
Multiplexed EPA
Figure 4-6. PTS Service (PTSSRV) Register
Reset State:
RI
TI
SSIO1
EPA1
EPA2
RI
TI
SSIO1
EPA1
EPA2
RI
TI
SSIO1
EPA1
EPA2
Function
Standard Vector
203CH
203AH
2038H
2036H
2034H
2032H
2030H
202EH
202CH
202AH
2028H
2026H
2024H
2022H
2020H
Address:
0006H
0000H
8
SSIO0
—
0
EPA3
EPA x
8
SSIO0
J1850ST
0
EPA3
EPA x
8
SSIO0
—
0
EPA3
EPA x
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