External Timing; Effect Of Clock Mode On Internal Clkout Frequency; Relationships Between Input Frequency, Clock Multiplier, And State Times - Intel 87C196CA Supplement To User’s Manual

XTAL1
(16 MHz)
f
PLLEN = 0
Internal
CLKOUT
f
PLLEN = 1
t = 31.25ns
Internal
CLKOUT
Figure 2-4. Effect of Clock Mode on Internal CLKOUT Frequency
Table 2-3. Relationships Between Input Frequency, Clock Multiplier, and State Times
F
1
XTAL
(Frequency PLLEN
on XTAL1)
4 MHz 0
8 MHz 0
12 MHz 0
16 MHz 0
20 MHz 0
4 MHz 1
8 MHz 1
10 MHz 1
2.4

EXTERNAL TIMING

You can control the output frequency on the CLKOUT pin by programming two uneraseable
PROM bits. Figure 2-5 illustrates the read-only USFR1, which reflects the state of the unerasable
PROM bits. You can select one of three frequencies: f/2, f/4, or f/8. As Figure 2-2 on page 2-3
shows, the configurable divider accepts the output of the clock generators (f/2) and further di-
vides that frequency to produce the desired output frequency. The CLK1:0 bits control the divisor
(divide f/2 by either 1, 2, or 4).
t = 62.5ns
Multiplier (Input Frequency to
the Divide-by-two Circuit)
1
1
1
1
1
2
2
2
ARCHITECTURAL OVERVIEW
T
XHCH
f
(Clock
Period)
4 MHz 250 ns
8 MHz 125 ns
12 MHz 83.5 ns
16 MHz 62.5 ns
20 MHz 50 ns
8 MHz 125 ns
16 MHz 62.5 ns
20 MHz 50 ns
A3376-01
t
State Time
500 ns
250 ns
167 ns
125 ns
100 ns
250 ns
125 ns
100 ns
2-5