Internal Structure For Ports 3 And 4 (Address/Data Bus) - Intel 87C196CA Supplement To User’s Manual

in using this pin. Be certain that your system meets the V
prevent inadvertent entry into ONCE mode or a test mode.
3. Following reset, P2.7/CLKOUT carries the strongly driven CLKOUT signal. It is not held
low. When P2.7/CLKOUT is configured as CLKOUT, it is always a complementary
output.
5.3

INTERNAL STRUCTURE FOR PORTS 3 AND 4 (ADDRESS/DATA BUS)

Figure 5-2 shows the logic of ports 3 and 4. Consult the datasheet for specifications on the amount
of current ports 3 and 4 can source and sink.
During reset, the active-low level of RESET# turns off Q1 and Q2 and turns on transistor Q4,
which weakly holds the pin low. Resistor R1 provides ESD protection for the pin. During normal
operation, the device controls the port through BUS CONTROL SELECT, an internal control sig-
nal.
When the device needs to access external memory, it clears BUS CONTROL SELECT, selecting
ADDRESS/DATA as the input to the multiplexer. ADDRESS/DATA then drives Q1 and Q2 as
complementary outputs.
When external memory access is not required, the device sets BUS CONTROL SELECT, select-
ing Px_REG as the input to the multiplexer. Px_REG then drives Q1 and Q2. If P34_DRV is set,
Q1 and Q2 are driven as complementary outputs. If P34_DRV is cleared, Q1 is disabled and Q2
is driven as an open-drain output requiring an external pull-up resistor. With the open-drain con-
figuration (BUS CONTROL SELECT set and P34_DRV cleared) and Px_REG set, the pin can
be used as an input. The signal on the pin is latched in the Px_PIN register. The pins can be read,
making it easy to see which pins are driven low by the device and which are driven high by ex-
ternal drivers while in open-drain mode.
I/O PORTS
specifications during reset to
IH
5-5