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8.6.4
Programming the J1850 Status (J_STAT) Register
The J1850 status register (Figure 8-19) provides the current status of the message and the four
interrupt sources associated with the J1850 protocol.
J_STAT
The J1850 status (J_STAT) register provides the current status of the message transfer, the receive
and transmit buffers, and the four interrupt sources associated with the J1850 protocol. This byte
register can be directly addressed through windowing . You must write to this register before
transmitting each message. Reading this register clears all bits except BUS_STAT.
7
IFR_RCV
BUS_CONT
Bit
Bit
Number
Mnemonic
7
IFR_RCV
6
BUS_CONT
5
BUS_STAT
4
BRK_RCV
3
OVR_UNDR
BUS_STAT
BRK_RCV
In-frame Response Received
This bit indicates whether the IFR byte has been received and is ready to
be read from the J1850 receiver (J_RX) register.
0 = no action
1 = IFR byte received
J1850 Bus Contention
This bit indicates whether bus contention has been detected and arbitration
has been lost.
0 = no action
1 = bus contention
J1850 Bus Status
This bit indicates whether a transmission or reception is in progress on the
J1850 bus.
0 = J1850 bus idle
1 = J1850 bus busy
Break Received
This bit indicates whether a BRK symbol has been detected on the J1850
bus.
0 = no action
1 = BRK symbol detected
Receive Overrun/Transmit Underflow Interrupt
This bit indicates whether a receive buffer overrun (OVR) or transmit buffer
underflow (UNDR) has occurred. An overrun occurs when a symbol is
received while both J_RX and JRX_BUF contain unread bytes. An
underflow occurs when a transmission is attempted while both J_TX and
JTX_BUF are empty.
0 = normal operation
1 = OVR or UNDR detected
Figure 8-19. J1850 Status (J_STAT) Register
J1850 COMMUNICATIONS CONTROLLER
Address:
Reset State:
OVR_UNDR
MSG_TX
Function
1F53H
00H
0
MSG_RX
J1850BE
8-21
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