Interrupt Registers; Interrupt Sources, Vectors, And Priorities - Intel 87C196CA Supplement To User’s Manual

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8XC196L X SUPPLEMENT

Table 4-1. Interrupt Sources, Vectors, and Priorities

Interrupt Source

Nonmaskable Interrupt

EXTINT Pin

Reserved

SIO Receive

SIO Transmit

SSIO Channel 1 Transfer

SSIO Channel 0 Transfer

J1850 Status (LB only)

Reserved (LA, LD)

Unimplemented Opcode

Software TRAP Instruction

J1850 Receive (LB only)

Reserved (LA, LD)

J1850 Transmit (LB only)

Reserved (LA, LD)

A/D Conv. Complete (LA, LB)

Reserved (LD)

EPA Capture/Compare 0

EPA Capture/Compare 1

EPA Capture/Compare 2

EPA Capture/Compare 3

EPA Capture/Compare 6–9,

EPA 0–3, 8–9 Overrun,

†††

EPA Compare 0–1

Timer 1 Overflow, &

Timer 2 Overflow

†

The NMI pin is not bonded out on the 8XC196L x . To protect against glitches, create a dummy interrupt

service routine that contains a RET instruction.

††

These interrupts are individually prioritized in the EPAIPV register. Read the EPA pending registers

(EPA_PEND and EPA_PEND1) to determine which source caused the interrupt.

†††

87C196LA, LB only. The 83C196LD has no EPA compare-only channels.

4.2