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8XC196L X SUPPLEMENT
The J1850 controller can handle network protocol functions including message frame sequenc-
ing, bit arbitration, in-frame response (IFR) messaging, error detection, and delay compensation.
The J1850 communications controller (Figure 8-2) consists of a control state machine (CSM),
symbol synchronization and timing (SST) circuitry, six control and status registers, transmit and
receive buffers, and an interrupt handler.
J1850ST
J1850RX
Interrupt
Handler
J1850TX
J_DLY
J_STAT
OVR
UNDR
J_TX
JTX_BUF
JRX_BUF
J_RX
J_CMD
J_CFG
Internal Clocking
Figure 8-2. J1850 Communications Controller Block Diagram
8-2
Bus Error
RX
TX
Error
Detection
Circuitry
Bit
Arbitration
Circuitry
Cyclic
Redundancy
Check Circuitry
CSM
J1850 Communications Controller
Delay
Compensator
Symbol
Encoder
Symbol
Digital
Decoder
Filter
Prescaler
TXJ1850
RXJ1850
SST
A5169-01
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