Block Diagram; Internal Timing; Xc196L X Block Diagram - Intel 87C196CA Supplement To User’s Manual

8XC196L X SUPPLEMENT
2.2

BLOCK DIAGRAM

Figure 2-1 is a simplified block diagram that shows the major blocks within the microcontroller.
Observe that the slave port peripheral does not exist on the 8XC196Lx.
I/O
Note:
The J1850 peripheral is unique to the 87C196LB device.
The A/D peripheral is unique to the 87C196LA, LB devices.
2.3

INTERNAL TIMING

The 87C196LA, LB clock circuitry (Figure 2-2) implements a phase-locked loop and clock mul-
tiplier circuitry, which can substantially increase the CPU clock rate while using a lower-frequen-
cy input clock. The clock circuitry accepts an input clock signal on XTAL1 provided by an
external crystal or oscillator. Depending on the value of the PLLEN pin, this frequency is routed
either through the phase-locked loop and multiplier or directly to the divide-by-two circuit. The
multiplier circuitry can double the input frequency (F
divide-by-two circuitry. The clock generators accept the divided input frequency (f/2) from the
divide-by-two circuit and produce two nonoverlapping internal timing signals, PH1 and PH2.
These signals are active when high.
This manual uses lowercase "f" to represent the internal clock frequency. For
the 87C196LA and LB, f is equal to either F
clock multiplier mode, which is controlled by the PLLEN input pin.
2-2
Optional
Core
(CPU, Memory ROM/
Controller)
OTPROM
Optional
Clock and
Code/Data
Power Mgmt.
RAM
SIO SSIO EPA
Figure 2-1. 8XC196L x Block Diagram
NOTE
Interrupt
Controller
Peripheral
Transaction
Server
J1850
A/D WDT
) before the frequency (f) reaches the
1
XTAL
or 2F , depending on the
1 1
XTAL XTAL
A5253-01