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8XC196L X SUPPLEMENT
prioritized interrupt
program memory
protected instruction
PSW
PTS
PTSCB
PTS control block
PTS cycle
PTS interrupt
PTS mode
PTS routine
PTS transfer
Glossary-8
NMI, stack overflow, or any maskable interrupt. Two
of the nonmaskable interrupts (unimplemented
opcode and software trap) are not prioritized; they
vector directly to the interrupt service routine when
executed.
A partition of memory where instructions can be
stored for fetching and execution.
An instruction that prevents an interrupt from being
acknowledged until after the next instruction
executes. The protected instructions are DI, EI,
DPTS, EPTS, POPA, POPF, PUSHA, and PUSHF.
Processor status word. The high byte of the PSW is
the status byte, which contains one bit that globally
enables or disables servicing of all maskable
interrupts, one bit that enables or disables the PTS,
and six Boolean flags that reflect the state of the
current program. The low byte of the PSW is the
INT_MASK register. A PUSHA or POPA instruction
saves or restores both bytes (PSW + INT_MASK); a
PUSHF or POPF saves or restores only the PSW.
Peripheral transaction server. The microcoded
hardware interrupt processor.
See PTS control block.
A block of data required for each PTS interrupt. The
microcode executes the proper PTS routine based on
the contents of the PTS control block.
The microcoded response to a single PTS interrupt
request.
Any maskable interrupt that is assigned to the PTS for
interrupt processing.
A microcoded response that enables the PTS to
complete a specific task quickly.
The entire microcoded response to multiple PTS
interrupt requests. The PTS routine is controlled by
the contents of the PTS control block.
The movement of a single byte or word from the
source memory location to the destination memory
location.
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