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F
XTAL1
XTAL1
XTAL2
Disable Oscillator
(Powerdown)
The rising edges of PH1 and PH2 generate the internal CLKOUT signal (Figure 2-3). The clock
circuitry routes separate internal clock signals to the CPU and the peripherals to provide flexibil-
ity in power management. It also outputs the CLKOUT signal on the CLKOUT pin. Because of
the complex logic in the clock circuitry, the signal on the CLKOUT pin is a delayed version of
the internal CLKOUT signal. This delay varies with temperature and voltage.
Disable
PLL
(Powerdown)
PLLEN
1
0
f
Divide by two
Circuit
f/2
Clock
Generators
f/2
Programmable
Divider
(CLK1:0)
Figure 2-2. Clock Circuitry (87C196LA, LB Only)
ARCHITECTURAL OVERVIEW
Phase
Filter
Comparator
Phase-locked
Oscillator
Phase-locked Loop
Clock Multiplier
Disable Clock Input (Powerdown)
To reset logic
Disable Clocks (Idle, Powerdown)
CPU Clocks (PH1, PH2)
Clock
Failure
Detection
Peripheral Clocks (PH1, PH2)
OSC
0
1
Disable Clocks (Powerdown)
CLKOUT
A5290-01
2-3
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