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8XC196L X SUPPLEMENT
8.6.2
Programming the J1850 Configuration (J_CFG) Register
The J1850 configuration register (Figure 8-17) selects the proper oscillator prescaler, initiates a
transmission break for debugging, invokes clock quadrupling operation, and selects the normal-
ization bit format.
J_CFG
The J1850 configuration (J_CFG) register selects the proper oscilator prescaler, initiates transmission
break for debug, invokes clock quadrupling operation, and selects the normalizartion bit format. This
byte register can be directly addressed through windowing . All J1850 bus activity is ignored until you
first write to this register.
7
NBF
IFR3
Bit
Bit
Number
Mnemonic
7
NBF
6
IFR3
5
4XM
4
TXBRK
3
RXPOL
Figure 8-17. J1850 Configuration (J_CFG) Register
8-18
4XM
TXBRK
Normalization Bit Format
This bit specifies which normalization bit (NB) format is to be used.
IFR with CRC Byte
0 =
active long NB
1 =
active short NB
Type 3 IFR Messaging
This bit selects type 3 IFR messaging, which supports the in-frame transfer
of an unspecified number of data bytes.
0 = normal operation
1 = type 3 IFR messaging
Oscillator Quadruple (4x) Mode
This bit allows the J1850 peripheral to operate at four times the normal bit
transfer rate (41.6 Kb/s versus 10.4 Kb/s).
0 = normal operation
1 = 4x mode operation
Transmission Break
This bit will terminate any transmission in progress by writing a break (BRK)
symbol to the bus.
0 = normal operation
1 = transmit BRK symbol onto bus
Receive Polarity
This bit changes the polarity of the receive symbol.
0 = normal operation – Rx input inverted
1 = receive polarity enabled – Rx input non-inverted
Address:
Reset State:
RXPOL
—
Function
IFR without CRC Byte
0 =
active short NB
1 =
active long NB
1F54H
00H
0
PRE1
PRE0
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