Interrupt Pending (Int_Pend) Register - Intel 87C196CA Supplement To User’s Manual

INT_PEND
When hardware detects an interrupt request, it sets the corresponding bit in the interrupt pending
(INT_PEND or INT_PEND1) registers. When the vector is taken, the hardware clears the pending bit.
Software can generate an interrupt by setting the corresponding interrupt pending bit.
7
LA —
7
LB J1850RX
7
LD —
Bit
Number
†
7:0 Any set bit indicates that the corresponding interrupt is pending. The interrupt bit is cleared
when processing transfers to the corresponding interrupt vector.
Bit Mnemonic Interrupt Description
J1850RX
J1850TX
AD
EPA0
EPA1
EPA2
EPA3
††
EPA x
††
EPA 6–9 capture/compare channel events, EPA 0–1 compare channel events
0–3 and 8–9 capture/compare overruns, and timer overflows can generate this shared
interrupt. Write the EPA mask registersto enable the interrupt sources; read the EPA
pending registers to determine which source caused the interrupt.
†††
87C196LA, LB only.
†
Bits 6–7 are reserved on the 87C196LA, and bits 5–7 are reserved on the 83C196LD. For
compatibility with future devices, write zeros to these bits.
Figure 4-3. Interrupt Pending (INT_PEND) Register
— AD EPA0
J1850TX AD EPA0
— — EPA0
J1850 Receive (LB only)
J1850 Transmit (LB only)
A/D Conversion Complete (LA, LB)
EPA Capture/Compare Channel 0
EPA Capture/Compare Channel 1
EPA Capture/Compare Channel 2
EPA Capture/Compare Channel 3
Shared EPA Interrupt
STANDARD AND PTS INTERRUPTS
Reset State:
EPA1 EPA2
EPA1 EPA2
EPA1 EPA2
Function
Address: 0009H
00H
0
EPA3 EPA x
0
EPA3 EPA x
0
EPA3 EPA x
†††
, EPA
4-5