Epa Pending Registers; Epa Interrupt Pending (Epa_Pend) Register; Epa Interrupt Pending 1 (Epa_Pend1) Register - Intel 87C196CA Supplement To User’s Manual

7.1.2

EPA Pending Registers

Figures 7-5 and 7-6 illustrate the EPA pending registers, EPA_PEND and EPA_PEND1, for the
8XC196Lx microcontroller family.
EPA_PEND
When hardware detects a pending EPA6–9 or OVR0–3, 8–9 interrupt request, it sets the
corresponding bit in the EPA interrupt pending register (EPA_PEND or EPA_PEND1). The EPAIPV
register contains a number that identifies the highest priority, active, shared interrupt source. When
EPAIPV is read, the EPA interrupt pending bit associated with the EPAIPV priority value is cleared.
15
Lx —
7
0VR2
Bit
Number
†
15:0 Any set bit indicates that the corresponding EPA x interrupt source is pending. The bit is
cleared when software reads the EPA interrupt priority vector register (EPAIPV).
†
Bits 2–5 and 14–15 are reserved on the 8XC196L x device family. For compatibility with future
devices, write zeros to these bits.
Figure 7-5. EPA Interrupt Pending (EPA_PEND) Register
EPA_PEND1
When hardware detects a pending EPA x interrupt, it sets the corresponding bit in the EPA interrupt
pending register (EPA_PEND or EPA_PEND1). The EPAIPV register contains a number that
identifies the highest priority, active, multiplexed interrupt source. When EPAIPV is read, the EPA
interrupt pending bit associated with the EPAIPV priority value is cleared.
7
— —
Bit
Number
7:4 Reserved; always write as zeros.
†
Any set bit indicates that the corresponding EPA x interrupt source is pending. The bit is
3:0
cleared when the EPA interrupt priority vector register (EPAIPV) is read.
†
87C196LA, LB only; reserved on 83C196LD.
Figure 7-6. EPA Interrupt Pending 1 (EPA_PEND1) Register
— EPA6 EPA7
OVR3 — —
Function
— — COMP0
Function
EVENT PROCESSOR ARRAY
Address:
Reset State:
EPA8 EPA9 OVR0
— — OVR8
Address:
Reset State:
† †
COMP1 OVRTM1
1FA2H
0000H
8
OVR1
0
OVR9
1FA6H
00H
0
OVRTM2
7-5