Enabling And Disabling The Expanded I/O Space; Programming Remapcfg Example; Setting The Ese Bit Code Example - Intel 386 User Manual

Intel386™ EX EMBEDDED MICROPROCESSOR USER'S MANUAL
4.5.2

Enabling and Disabling the Expanded I/O Space

The Intel386 EX processor's expanded I/O space is enabled by a specific write sequence to I/O
addresses 22H and 23H (Figure 4-4). Once the expanded I/O space is enabled, internal peripher-
als (timers, DMA, interrupt controllers and serial communication channels) can be mapped out
of DOS I/O space (using the REMAPCFG register) and registers associated with other internal
peripherals (such as the chip-select unit, power management unit, watchdog timer) can be access-
ed.
4.5.2.1

Programming REMAPCFG Example

The expanded I/O space enable (ESE) bit in the REMAPCFG register can be set only by three
sequential write operations to I/O addresses 22H and 23H as described in Figure 4-4. Once ESE
is set, REMAPCFG and all the on-chip registers in the expanded I/O address range 0F000H–
0FFFFH can be accessed. The remap bits in REMAPCFG are still in effect even after the ESE bit
is cleared.
;;disable interrupts
CLI
; Enable expanded I/O space of Intel386(tm) EX processor
; for peripheral initialization.
MOV AX, 08000H
OUT 23H, AL
XCHG AL, AH
OUT 22H, AL
OUT 22H, AX
;; at this point PC/AT peripherals can be mapped out
;; For example,
;; Map out the on-chip DMA channels from the DOS I/O space (slot 0)
MOV AL, 04H
OUT 22H, AL
; Disables expanded I/O space
MOV AL, 00H
OUT 23H, AL
;; Re-enable Interrupts
STI
The REMAPCFG register is write-protected until the expanded I/O space is enabled. When the
enabling write sequence is executed, it sets the ESE bit. A program can check this bit to see
whether it has access to the expanded I/O space registers. Clearing the ESE bit disables the ex-
panded I/O space. This can be done by a byte write with a value of 0 to I/O address 23H. This
again locks the REMAPCFG register and makes it read-only.
4-8
; Enable expanded I/O space
; and unlock the re-map bits
Figure 4-4. Setting the ESE Bit Code Example