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Table A-2. Description of Signals Available at the Device Pins (Sheet 6 of 6)
Signal
Type
TMS
I
Test Mode Select:
Controls the sequence of the test-logic unit's TAP controller
states. Sampled on the rising edge of TCK.
TRST#
ST
Test Reset:
Resets the test-logic unit's TAP controller. Asynchronously
clears the data registers and initializes the instruction
register to 0010 (the IDCODE instruction opcode).
TXD1
O
Transmit Data:
TXD0
Transmits serial data from the corresponding SIO channel.
UCS#
O
Upper Chip-select:
Activated when the address of a memory or I/O bus cycle is
within the address region programmed by the user.
V
P
System Power:
CC
Provides the nominal DC supply input. Connected
externally to a V
V
G
System Ground:
SS
Provides the 0 volt connection from which all inputs and
outputs are measured. Connected externally to a ground
board plane.
WDTOUT
O
Watchdog Timer Output:
Indicates that the watchdog timer has expired.
W/R#
O
Write/Read:
Indicates whether the current bus cycle is a write cycle or a
read cycle.
WR#
O
Write Enable:
Indicates that the current bus cycle is a write cycle.
Name and Description
board plane.
CC
SIGNAL DESCRIPTIONS
Multiplexed With
(Alternate
Function)
—
—
DACK1#
P2.6
—
—
—
—
—
—
A-7
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