Intel 386 User Manual page 673

Intel386™ EX EMBEDDED MICROPROCESSOR USER'S MANUAL
DOS-compatible Mode
Edge-triggered
Enhanced DOS Mode
Expanded Address Space
ICU
Idle Mode
Interrupt Latency
Glossary-2
be mapped into this space. In this manual, the terms
DOS address and PC/AT address are synonymous.
The addressing mode in which the internal timer,
interrupt controller, serial I/O ports, and DMA
controller are mapped into the DOS address space.
This mode decodes only the lower 10 address bits, so
the expanded address space is inaccessible.
The mode in which the interrupt controller recognizes
a rising edge (low-to-high transition) on an interrupt
request signal as an interrupt request. The internal
peripherals use edge-triggered interrupt requests; this
is compatible with the PC/AT bus specification.
External peripherals can use either edge-triggered or
level-sensitive interrupt requests.
The addressing mode in which the internal timer,
interrupt controller, serial I/O ports, and DMA
controller are mapped into both the DOS address
space and the expanded address space. This mode
decodes all 16 address bits. All internal peripherals
can be accessed in the expanded address space; the
internal timer, interrupt controller, serial I/O ports,
and DMA controller can also be accessed in the DOS
address space.
Addresses 0F000H–0F8FFH. All internal peripheral
registers reside in this space. The internal timer,
interrupt controller, serial I/O ports, and DMA
controller can also be mapped into DOS (or PC/AT)
address space.
Interrupt control unit. The internal peripheral that
receives interrupt requests from internal peripherals
and external pins, resolves priority, and presents the
requests to the CPU. The ICU is functionally identical
to two industry-standard 82C59A programmable
interrupt controllers connected in cascade.
The power conservation mode that freezes the core
clocks but leaves the peripheral clocks running.
The delay between the time that the master 82C59A
presents an interrupt request to the CPU and the time
that the interrupt acknowledge cycle begins.