Intel 386 User Manual page 687

INTEL386™ EX MICROPROCESSOR USER'S MANUAL
13-16 13-24
SSIOTBUF, ,
TBRn, 11-15, 11-23, D-61
5-13 10-4
TMRCFG, ,
10-4 10-25
TMRCON, ,
TMRn, 10-4, 10-26, 10-29, 10-32, D-64, D-65
14-14 14-17
UCSADH, ,
14-14 14-18
UCSADL, ,
14-14 14-19
UCSMSKH, ,
14-14 14-20
UCSMSKL, ,
17-7
WDTCLR,
17-7 17-8
WDTCNTH, ,
17-7 17-8
WDTCNTL, ,
17-7 17-10
WDTRLDH, ,
17-7 17-10
WDTRLDL, ,
17-7
WDTSTATUS, ,
17-4
reload event,
1-5
Reserved bits, defined,
Reset
8-11
considerations,
B-4
CPU-only,
Resume instruction (RSM),
RSM, See Resume instruction
S
Scratch pad registers
SCRn, 11-32, D-56
Segment Descriptor Cache,
3-4
Segmentation Unit, ,
8-1 8-2 11-1
SERCLK, – ,
13-5 13-18
,
11-1 11-45
Serial I/O unit, –
11-2
block diagram,
5-14
configuring,
departure from PC/AT architecture,
5-3 5-5
DMA service, –
11-4 11-14
operation, –
baud-rate generator,
data transmission process flow,
11-12
diagnostic mode,
11-13
interrupt sources,
11-12
modem control,
11-9 11-10
receiver, –
11-6
transmitter, –
11-1 11-3
overview, –
Index-8
D-61
,
10-21 D-62
, ,
10-28 10-30 D-63
, , ,
D-8
,
D-9
,
D-10
,
D-11
,
D-67
,
D-67
,
D-68
,
D-68
,
17-9 D-69
,
7-15
3-5
3-5
11-4 11-21 13-1
, , , ,
B-3
11-4 11-5
–
11-8
11-8
programming
accessing multiplexed registers,
11-32
considerations,
11-22
DLHn register,
11-22
DLLn register,
11-27
IERn register,
11-28
IIRn register,
LCRn, 11-25, D-36
11-25
LCRn register,
LSRn, 11-26, D-37
11-26
LSRn register,
MCRn, 11-30, D-38
11-29
MCRn register,
modem control signals,
MSRn, 11-31, D-39
11-31
MSRn register,
11-18
P1CFG register,
11-19
P2CFG register,
11-20
P3CFG register,
PINCFG register,
RBRn, 11-24, D-52
11-24
RBRn register,
11-32
SCRn register,
5-17 11-21
SIOCFG, ,
SIOCFG register,
TBRn, 11-23, D-61
11-23
TBRn register,
4-19
register addresses,
11-15 11-16
registers, –
11-3
signals,
1-5
Set, defined,
A-1
Signal descriptions,
Signal names, notational conventions,
SIO, See Serial I/O unit
SMM, See System management mode
SMM, see System Management Mode,
7-2
SMRAM,
chip-select unit support for,
7-14
state dump area,
Specific EOI command,
SSIO, See Synchronous serial I/O unit
Synchronous serial I/O unit,
5-18
configuring,
design considerations,
5-3
DMA service,
master/slave mode arrangements,
11-16
11-30
–
11-29 11-30
–
11-17
13-18 D-57
, ,
11-21
4-20 D-5 D-6
, , ,
A-10
–
1-4
7-3
7-12
9-14
13-1 13-25
–
13-25
13-2 13-3
–