Intel 386 User Manual page 674

Interrupt Response Time
Interrupt Resolution
ISR
JTAG
Level-sensitive
LSB
NonDOS Mode
Nonintrusive DOS Mode
Normally not-ready
The amount of time required to complete an interrupt
acknowledge cycle and transfer program control to
the interrupt service routine.
The delay between the time that the interrupt
controller receives an interrupt request and the time
that the master 82C59A presents the request to the
CPU.
Interrupt service routine. A user-supplied software
routine designed to service specific interrupt requests.
Joint Test Action Group. The IEEE technical
subcommittee that developed the testability standard
published as Standard 1149.1-1990, IEEE Standard
Test Access Port and Boundary-Scan Architecture,
and its supplement, Standard 1149.1a-1993. The test-
logic unit is fully compliant with this standard.
The mode in which the interrupt controller recognizes
a high level (logic one) on an interrupt request signal
as an interrupt request. Unlike an edge-triggered
interrupt request, a level-sensitive interrupt request
will continue to generate interrupts as long as it is
asserted.
Least-significant bit of a byte or least-significant byte
of a word.
The addressing mode in which the internal timer,
interrupt controller, serial I/O ports, and DMA
controller are mapped into the expanded address
space. This mode decodes all 16 address bits. All
internal peripherals can be accessed only in the
expanded address space.
The addressing mode in which the internal timer,
interrupt controller, serial I/O ports, and DMA
controller can be individually mapped out of the DOS
address space and replaced by the corresponding
external peripherals. This mode decodes only the
lower 10 address bits, so the expanded address space
is inaccessible.
The term normally not-ready refers to a system in
which a bus cycle continues until the accessed device
asserts READY#.
GLOSSARY
Glossary-3