Dmacmd2; D.12 Dmacmd2 - Intel 386 User Manual

D.12 DMACMD2

DMA Command 2

DMACMD2

(write only)
7
— —
Bit Bit
Number Mnemonic
7–4 —
3–2 PL1:0
1 ES
0 DS
— —
Reserved; for compatibility with future devices, write zeros to these bits.
Low Priority Level Set:
Use these bits to assign a particular bus request to the lowest priority
level in fixed priority mode.
00 = Assigns channel 0's request (DREQ0) to the lowest priority level
01 = Assigns channel 1's request (DREQ1) to the lowest priority level
10 = Assigns the external bus master request (HOLD) to the lowest
priority level
11 = Reserved
EOP# Sampling:
0 = Causes the DMA to sample the EOP# input asynchronously.
1 = Causes the DMA to sample the end-of-process (EOP#) input
synchronously.
DREQ n Sampling:
0 = Causes the DMA to sample the DREQ n inputs asynchronously.
1 = Causes the DMA to sample the channel request (DREQ n ) inputs
synchronously.
SYSTEM REGISTER QUICK REFERENCE
Expanded Addr: F01AH
ISA Addr: —
Reset State: 08H
PL1 PL0
Function
0
ES DS
D-17