Intel 386 User Manual page 680

1-3
#, defined,
9-1
82C59A,
A
6-1
Address bus,
Address lines
3-1
new,
Address space
configuration register,
4-3
expanded I/O,
enabling/disabling,
I/O decoding techniques,
I/O for PC/AT systems,
4-15
peripheral registers,
4-9
Addressing modes, –
DOS-compatible mode,
4-11
enhanced DOS mode,
4-11 4-14
nonDOS mode, ,
nonintrusive DOS mode,
B-2
AEN signal, deriving,
9-9
AEOI mode,
6-9
aligned data transfers,
2-1
Applications, typical,
2-1
Architectural overview,
1-4
Assert, defined,
Asynchronous serial I/O unit, See Serial I/O unit
Automatic end of interrupt (AEOI) mode,
B
11-4
Baud-rate generator,
BIU, See Bus interface unit
Block diagram
clock and power management unit,
12-2
DMA unit,
16-2
I/O port,
18-2
JTAG test-logic unit,
11-2
SIO unit,
baud-rate generator clock,
modem control signals,
11-9
receiver,
11-7
transmitter,
4-6
4-8
4-6
4-2
4-14
4-9 4-10
–
4-13
,
4-11 4-12
,
B-3
–
2-4
–
9-9
11-5 13-5 13-6
– , –
8-2
11-4
11-29
13-2 13-3
SSIO unit, ,
baud-rate generator clock,
10-2
timer/counter unit,
17-2
watchdog timer unit,
18-2
BOUND,
18-1
Boundary scan register,
8-12
Built-in self-test,
Bulletin board system (BBS),
Bus arbiter
4-15
register addresses,
Bus arbiter, configuration,
12-9
Bus control arbitration,
Bus cycle length adjustments for overlapping
chip-select regions,
6-3
Bus interface pins,
3-4, 6-1
Bus interface unit,
6-1
address bus,
6-2
bus control pins,
6-13 6-33
bus cycles, –
6-31 6-33
BS8, –
6-26
halt/shutdown,
interrupt acknowledge,
6-19 6-23
pipelined, –
6-13 6-14
read, –
6-28 6-30
refresh, –
6-16 6-18
write, –
6-34 6-35
bus lock, –
LOCK# signal duration,
locked cycle activators,
locked cycle timing,
6-5 6-14
bus operation, –
6-8
bus state diagram, ,
6-7 6-8
bus states, –
bus status
6-5
definitions,
6-1
data bus,
transfers and operand alignment,
6-20 6-35
HOLD/HLDA, ,
departures from PC/AT architecture,
HOLD signal latency,
6-36
timing,
INDEX
13-5
1-7
D-1
,
5-3
14-11 14-12
,
6-37
–
6-27
–
6-23 6-25
–
6-35
6-34
6-34
6-20
6-9
B-4
6-37
Index-1