Intel 386 User Manual page 681

INTEL386™ EX MICROPROCESSOR USER'S MANUAL
operation during idle mode,
6-1 6-3
overview, –
6-8
pipelining,
6-10
ready logic,
See also Bus control arbitration
6-3 6-4
signals, –
Bus signals, departures from PC/AT
B-2
architecture,
Bus size control for chip-selects,
18-2
BYPASS,
C
CAS#-before-RAS# refresh,
14-1–14-24
Chip-select unit,
14-2 14-12
operation, –
bus cycle length adjustments,
bus cycle length control,
14-11
bus size control,
defining a channel's address block,
14-9
overlapping regions,
system management mode support,
14-1
overview,
14-13 14-20
programming, –
14-22
considerations,
14-17
CSnADH, ,
14-18
CSnADL, ,
14-19
CSnMSKH,
14-20
CSnMSKL,
14-16
P2CFG register,
PINCFG register,
14-17
UCSADH,
14-18
UCSADL, ,
14-19
UCSMSKH,
14-20
UCSMSKL,
4-17
register addresses,
14-14 14-20
registers, –
14-13
signals,
1-5
Clear, defined,
Clock and power management unit,
clock generation logic,
controlling power management modes,
controlling PSCLK frequency,
design considerations
powerdown considerations,
reset considerations,
Index-2
8-5
B-3
–
14-11
15-1 15-12
,
14-12
14-11
14-2
–
14-11
14-10
D-8
D-9
D-10
,
D-11
,
14-15
D-8
,
D-9
D-10
,
D-11
,
D-3
,
8-1 8-13
–
8-1 8-3
–
8-8
8-7
8-13
8-11
8-9
idle mode,
8-1 8-7
overview, –
power management logic,
8-10
powerdown mode,
8-6
registers,
8-7
CLKPRS,
8-8
PWRCON,
8-11
reset considerations,
8-6
signals,
8-3
synchronization,
8-9 8-11
timing diagram, –
Clock management
4-19
register addresses,
8-3
Clock synchronization,
3-4
Code Prefetch Unit,
1-7
CompuServe forums,
Configuration
5-3 5-5
bus arbiter, –
5-21 5-22
core, –
5-1 5-37
device, –
5-3
DMA controller,
5-28 5-33
example, –
5-23 5-25 5-26
I/O ports, , ,
11-18 11-19 11-20 14-16
, , ,
D-45
5-7
interrupt control unit,
5-23 5-27
pins, –
5-22
Port92,
5-28
procedure,
5-3
refresh control unit,
5-14
serial I/O unit,
serial synchronous I/O unit,
5-11
timer/counter unit,
5-34 5-37
worksheets, –
Core
5-21 5-22
configuring, –
2-1
Core architecture,
Core overview
3-1
CX enhancements,
3-2
Internal architecture,
5-22 B-4
CPU-only reset, ,
CSU, See Chip-select unit
1-6
Customer service,
CX internal architecture,
8-3 8-5
–
D-5
,
5-27 9-18 10-22
, , , ,
D-43 D-44
, , ,
5-18
3-2