Intel 386 User Manual page 233

Intel386™ EX EMBEDDED MICROPROCESSOR USER'S MANUAL
Real/Protected Mode
No changes required.
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int InitICU(BYTE MstrMode, BYTE MstrBase, BYTE MstrCascade, BYTE SlaveMode,
BYTE SlaveBase, BYTE MstrPins, BYTE SlavePins)
{
BYTE icw, cfg_pins;
/* Program Slave ICU */
_IRQ_SlaveBase_ = SlaveBase & 0xf8;
_SetEXRegByte(ICW1S, 0x11 | SlaveMode);// Set slave triggering
_SetEXRegByte(ICW2S, _IRQ_SlaveBase_); // Set slave base interrupt type,
_SetEXRegByte(ICW3S, 0x2);
_SetEXRegByte(ICW4S, 0x1);
/* Program Master ICU */
_IRQ_MstrBase_ = MstrBase & 0xf8;
_CascadeBits_ = MstrCascade | 0x4;
icw = (MstrMode & ICU_TRIGGER_LEVEL) ? 0x19 : 0x11;
_SetEXRegByte(ICW1M, icw);
_SetEXRegByte(ICW2M, _IRQ_MstrBase_); // Set master base interrupt
_SetEXRegByte(ICW3M, _CascadeBits_);
icw = (MstrMode & ~ICU_TRIGGER_LEVEL) | 1;// Set bit 0 and remove
_SetEXRegByte(ICW4M, icw);
/* Program chip configuration registers */
cfg_pins = _GetEXRegByte(INTCFG);
if( (MstrCascade & 0xfb) != 0 )
cfg_pins |= 0x80;
cfg_pins |= SlavePins;
_SetEXRegByte(INTCFG, SlavePins);
cfg_pins = _GetEXRegByte(P3CFG);
_SetEXRegByte(P3CFG, cfg_pins | MstrPins);// Set Master external
return E_OK;
}/* InitICU */
9-34
// least 3-bit must be 0
// Set slave ID
// Set bit 0 to guarantee operation
// Set master triggering
// type, least 3-bit must be 0
// Set master cascade pins,
// Make sure IR2 set for Cascade
// Trigger_level bit (in ICW1)
// Set slave IDs in master
// bit 2 (IR2) is internal,
// external signals not required
// for just IR2
// Using external slaves,
// therefore enable Cascade signals
// Set Slave external interrupt pins
// Preserve other set bits
// interrupt pins