Intel 386 User Manual page 532

Table A-2. Description of Signals Available at the Device Pins (Sheet 2 of 6)
Signal Type
CTS1# I Clear to Send:
CTS0#
Indicates that the modem or data set is ready to exchange
data with the SIO channel.
D15:0 I/O Data Bus:
Inputs data during memory read, I/O read, and interrupt
acknowledge cycles; outputs data during memory write and
I/O write cycles. During reads, data is latched during the
falling edge of phase 2 of T2, T2P, or T2i. During writes, this
bus is driven during phase 2 of T1 and remains active until
phase 2 of the next T1, T1P, or Ti.
DACK1# O DMA Channel Acknowledge:
DACK0#
Indicates that the DMA channel is ready to service the
requesting device. An external device uses the DRQ n pin to
request DMA service; the DMA uses the DACK n pin to
indicate that the request is being serviced.
D/C# O Data/Control:
Indicates whether the current bus cycle is a data cycle
(memory or I/O read or write) or a control cycle (interrupt
acknowledge, halt/shutdown, or code fetch).
DCD1# I Data Carrier Detect:
DCD0#
Indicates that the modem or data set has detected the SIO
channel's data carrier.
DRQ1 I DMA External Request:
DRQ0
Indicates that an external device requires DMA service.
DSR1# I Data Set Ready:
DSR0#
Indicates that the modem or data set is ready to establish
the communications link with the SIO channel.
DTR1# O Data Terminal Ready:
DTR0#
Indicates that the SIO channel is ready to establish a
communications link with the modem or data set.
EOP# I/OD End-of-process:
As an input, this signal terminates a DMA transfer. As an
ouput, it indicates that a DMA transfer has completed.
ERROR# I Error:
Indicates the the math coprocessor has an error condition.
FLT# I Float:
Forces all bidirectional and output signals except TDO to a
high-impedance state.
HLDA O Hold Acknowledge:
Indicates that the processor has relinquished local bus
control to another bus master in response to a HOLD
request.
Name and Description
SIGNAL DESCRIPTIONS
Multiplexed With
(Alternate
Function)
EOP#
P2.7
—
TXD1
CS5#
—
DRQ0
P1.0
RXD1
DCD1#
STXCLK
P1.3
SRXCLK
P1.2
CTS1#
TMROUT2
—
P1.7
A-3