Figure
6-16
Intel386 EX Processor to SRAM/FLASH Interface.....................................................6-41
6-17
Intel386 EX Processor to PSRAM Interface ...............................................................6-42
6-18
Intel386 EX Processor to Paged DRAM Interface......................................................6-43
6-19
Intel386 EX Processor and Non-Paged DRAM Interface ...........................................6-44
7-1
Standard SMI# .............................................................................................................7-5
7-2
SMIACT# Latency .......................................................................................................7-6
7-3
SMI# During HALT ......................................................................................................7-8
7-4
7-5
SMI# Timing ...............................................................................................................7-10
7-6
Interrupted SMI# Service............................................................................................7-11
7-7
HALT During SMM Handler........................................................................................7-12
8-1
8-2
Clock Synchronization ..................................................................................................8-3
8-3
8-4
Clock Prescale Register (CLKPRS) .............................................................................8-7
8-5
Power Control Register (PWRCON).............................................................................8-8
8-6
Timing Diagram, Entering and Leaving Idle Mode .......................................................8-9
8-7
8-8
9-1
Interrupt Control Unit Configuration..............................................................................9-3
9-2
9-3
Interrupt Process - Master Request from Non-slave Source .....................................9-11
9-4
9-5
9-6
Port 3 Configuration Register (P3CFG)......................................................................9-18
9-7
Interrupt Configuration Register (INTCFG).................................................................9-19
9-8
Initialization Command Word 1 Register (ICW1)........................................................9-20
9-9
Initialization Command Word 2 Register (ICW2)........................................................9-21
9-10
Initialization Command Word 3 Register (ICW3 - Master).........................................9-22
9-11
9-12
Initialization Command Word 4 Register (ICW4)........................................................9-24
9-13
Operation Command Word 1 (OCW1) .......................................................................9-25
9-14
Operation Command Word 2 (OCW2) .......................................................................9-26
9-15
Operation Command Word 3 (OCW3) .......................................................................9-27
9-16
Poll Status Byte (POLL) .............................................................................................9-28
9-17
Interrupt Acknowledge Cycle......................................................................................9-29
9-18
Spurious Interrupts .....................................................................................................9-30
9-19
10-1
10-2
10-3
10-4
10-5
10-6
FIGURES
CONTENTS
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