Intel386™ EX MICROPROCESSOR USER'S MANUAL
Figure
13-7
13-8
Transmit Data by Polling ............................................................................................13-9
13-9
13-10
Transmitter Master Mode, Single Word Transfer (Enabled when Clock is High) .....13-11
13-11
Transmitter Master Mode, Single Word Transfer (Enabled when Clock is Low) ......13-11
13-12
Receive Data by Polling ...........................................................................................13-13
13-13
13-14
13-15
Pin Configuration Register (PINCFG).......................................................................13-17
13-16
SIO and SSIO Configuration Register (SIOCFG).....................................................13-18
13-17
Clock Prescale Register (CLKPRS) .........................................................................13-19
13-18
SSIO Baud-rate Control Register (SSIOBAUD) .......................................................13-20
13-19
SSIO Baud-rate Count Down Register (SSIOCTR)..................................................13-21
13-20
SSIO Control 1 Register (SSIOCON1) .....................................................................13-22
13-21
SSIO Control 2 Register (SSIOCON2) .....................................................................13-23
13-22
SSIO Transmit Holding Buffer (SSIOTBUF).............................................................13-24
13-23
SSIO Receive Holding Buffer (SSIORBUF) .............................................................13-25
14-1
14-2
14-3
14-4
Pin Configuration Register (PINCFG).......................................................................14-15
14-5
Port 2 Configuration Register (P2CFG)....................................................................14-16
14-6
14-7
14-8
14-9
15-1
15-2
Refresh Clock Interval Register (RFSCIR) .................................................................15-7
15-3
Refresh Control Register (RFSCON) .........................................................................15-8
15-4
Refresh Base Address Register (RFSBAD) ...............................................................15-9
15-5
Refresh Address Register (RFSADD) ......................................................................15-10
15-6
15-7
15-8
16-1
I/O Port Block Diagram...............................................................................................16-2
16-2
16-3
16-4
16-5
16-6
17-1
17-2
17-3
xx
FIGURES
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