Intel386™ EX MICROPROCESSOR USER'S MANUAL
Figure
10-7
10-8
10-9
10-10
10-11
10-12
10-13
10-14
10-15
10-16
10-17
10-18
10-19
10-20
10-21
10-22
10-23
Port 3 Configuration Register (P3CFG)....................................................................10-22
10-24
Pin Configuration Register (PINCFG).......................................................................10-23
10-25
10-26
10-27
10-28
10-29
10-30
11-1
11-2
SIO n Transmitter ........................................................................................................11-7
11-3
11-4
SIO n Receiver ............................................................................................................11-9
11-5
11-6
11-7
Pin Configuration Register (PINCFG).......................................................................11-17
11-8
11-9
Port 2 Configuration Register (P2CFG)....................................................................11-19
11-10
11-11
SIO and SSIO Configuration Register (SIOCFG).....................................................11-21
11-12
Divisor Latch Registers (DLL n and DLH n ) ...............................................................11-22
11-13
Transmit Buffer Register (TBR n ) ..............................................................................11-23
Receive Buffer Register (RBR n )...............................................................................11-24
11-14
Serial Line Control Register (LCR n ) .........................................................................11-25
11-15
Serial Line Status Register (LSR n )...........................................................................11-26
11-16
Interrupt Enable Register (IER n ) ..............................................................................11-27
11-17
Interrupt ID Register (IIR n ) .......................................................................................11-28
11-18
11-19
11-20
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FIGURES
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