Intel 386 User Manual page 654

Table E-1. Instruction Set Summary (Sheet 16 of 19)
Instruction
INTO:
Via interrupt or Trap Gate
To same privilege level
Via Interrupt or Trap Gate
To different privilege level
From 286 task to 286 TSS via Task Gate
From 286 task to Intel 386 SX CPU TSS via Task Gate
From 286 task to virtual 8086 mode via Task Gate
From Intel386 SX CPU task to 286 TSS via Task Gate
From Intel386 SX CPU task to Intel 386 SX CPU TSS via task gate
From Intel386 SX CPU task to virtual 8086 mode via Task Gate
From virtual 8086 mode to 286 TSS via Task Gate
From virtual 8086 mode to Intel 386 SX CPU TSS via task gate
From virtual 8086 mode to privilege level 0 via trap gate or interrupt gate
BOUND:
Via interrupt or Trap Gate
To same privilege level
Via Interrupt or Trap Gate
To different privilege level
From 286 task to 286 TSS via Task Gate
From 286 task to Intel 386 SX CPU TSS via Task Gate
From 286 task to virtual 8086 mode via Task Gate
From Intel386 SX CPU task to 286 TSS via Task Gate
From Intel386 SX CPU task to Intel 386 SX CPU TSS via task gate
From Intel386 SX CPU task to virtual 8086 mode via Task Gate
From virtual 8086 mode to 286 TSS via Task Gate
From virtual 8086 mode to Intel 386 SX CPU TSS via task gate
From virtual 8086 mode to privilege level 0 via trap gate or interrupt gate
INTERRUPT RETURN
IRET = Interrupt return 1 1 0 0 1 1 1 1
Protected Mode Only
(IRET)
To same privilege level (within task)
Format
INSTRUCTION SET SUMMARY
Clock Count Notes
Real Pro- Real
Ad- tected Ad-
dress Virtual dress
Mode Ad- Mode
or dress or
Virtual Mode Virtual
8086 8086
Mode Mode
71
111
384
411
328
Intel386
DX
413
329
391
418
223
71
111
358
388
335
368
398
347
368
398
223
24
42
Pro-
tected
Virtual
Ad-
dress
Mode
g, j, k, r
g, j, k, r
g, j, k, r
g, j, k, r
g, j, k, r
g, j, k, r
g, j, k, r
g, j, k, r
g, j, k, r
g, j, k, r
g, j, k, r
g, j, k, r
g, j, k, r
g, j, k, r
g, j, k, r
g, j, k, r
g, j, k, r
g, j, k, r
g, j, k, r
g, j, k, r
g, h, j, k,
r
g, h, j, k,
r
E-17