Intel 386 User Manual page 676

State Time (or State)
TAP
TCU
Test-logic Unit
UART
WDT
communications. The transmitter and receiver can
operate independently (with different clocks) to
provide full-duplex communication.
The basic time unit of the device; the combined
period of the two internal timing signals, PH1 and
PH2. With a 50 MHz external clock, one state time
equals 80 ns. Because the device can operate at many
frequencies, this manual defines time requirements in
terms of state times rather than in specific units of
time.
Test access port. The dedicated input and output pins
through which a tester communicates with the test-
logic unit. A major component of the JTAG standard.
Timer/counter unit. The internal peripheral that
provides three independent 16-bit down-counters.
The module that facilitates testing of the device logic
and interconnections between the device and the
board. This module is fully compliant with IEEE
Standard 1149.1, commonly called the JTAG
standard.
Universal asynchronous receiver and transmitter. A
part of the SIO unit.
Watchdog timer. An internal, 32-bit down-counter
that can operate as a general-purpose timer, a software
watchdog timer, or a bus monitor.
GLOSSARY
Glossary-5