Intel 386 User Manual page 117

Intel386™ EX EMBEDDED MICROPROCESSOR USER'S MANUAL
Table 6-1. Bus Interface Unit Signals (Sheet 2 of 2)
Device Pin or
Signal Internal Signal
only
M/IO# Device pins
D/C#
W/R#
REFRESH#
NA# Device pin
RD# Device pin
READY# Device pin
WR# Device pin
6-4
Bus Cycle Definition Signals (Memory/IO, Data/Control, Write/Read,
and Refresh):
These four status outputs define the current bus cycle type, as shown
in Table 6-2.
Next Address:
Requests address pipelining.
Read Enable:
Indicates that the current bus cycle is a read cycle and the data bus is
able to accept data.
Ready:
This bidirectional pin is used to terminate the current bus cycle. The
processor drives READY# when LBA# is active. The processor
samples the READY# pin at the falling edge of Phase 2 of T2, T2P or
T2i.
The READY# signal is also used to deassert the WR# signal (Refer to
"Write Cycle" on page 6-16).
Write Enable:
Indicates that the current bus cycle is a write cycle and valid data is
present on the data bus.
Description