Intel 386 User Manual page 533

Intel386™ EX EMBEDDED MICROPROCESSOR USER'S MANUAL
Table A-2. Description of Signals Available at the Device Pins (Sheet 3 of 6)
Signal Type
HOLD I Hold Request:
An external bus master asserts HOLD to request control of
the local bus. The processor finishes the current nonlocked
bus transfer, releases the bus signals, and asserts HLDA.
INT9 I Interrupt Requests:
INT8
These maskable inputs cause the processor to suspend
INT7
execution of the current program and execute an interrupt
INT6
acknowledge cycle.
INT5
INT4
INT3
INT2
INT1
INT0
LBA# O Local Bus Access:
Indicates that the processor provides the READY# signal
internally to terminate a bus transaction. This signal is
active when the processor accesses an internal peripheral
or when the chip-select unit provides the READY# signal for
an external peripheral.
LOCK# O Bus Lock:
Prevents other bus masters from gaining control of the bus.
M/IO# O Memory/IO:
Indicates whether the current bus cycle is a memory cycle
or an I/O cycle.
NA# I Next Address:
Requests address pipelining.
NMI ST Nonmaskable Interrupt Request:
Causes the processor to suspend execution of the current
program and execute an interrupt acknowledge cycle.
PEREQ I Processor Extension Request:
Indicates that the math coprocessor has data to transfer to
the processor.
P1.7 I/O Port 1:
P1.6
General-purpose, bidirectional I/O port.
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
A-4
Name and Description
Multiplexed With
(Alternate
Function)
P1.6
P3.0/TMROUT0
P3.1/TMROUT1
TMRGATE1
TMRCLK1
TMRGATE0
TMRCLK0
P3.5
P3.4
P3.3
P3.2
—
P1.5
—
—
—
TMRCLK2
HLDA
HOLD
LOCK#
RI0#
DSR0#
DTR0#
RTS0#
DCD0#