Intel 386 User Manual page 17

Intel386™ EX MICROPROCESSOR USER'S MANUAL
Figure
2-1 Intel386™ EX Embedded Processor Block Diagram ...................................................2-2
3-1 Instruction Pipelining ....................................................................................................3-2
3-2 The Intel386™ CX Processor Internal Block Diagram .................................................3-3
4-1 PC/AT I/O Address Space (10-bit Decode) ..................................................................4-3
4-2 Expanded I/O Address Space (16-bit Decode) ............................................................4-4
4-3 Address Configuration Register (REMAPCFG)............................................................4-7
4-4 Setting the ESE Bit Code Example ..............................................................................4-8
4-5 DOS-Compatible Mode ..............................................................................................4-10
4-6 Example of Nonintrusive DOS-Compatible Mode ......................................................4-12
4-7 Enhanced DOS Mode ................................................................................................4-13
4-8 NonDOS Mode ...........................................................................................................4-14
5-1 Peripheral and Pin Connections...................................................................................5-2
5-2 Configuration of DMA, Bus Arbiter, and Refresh Unit ..................................................5-5
5-3 DMA Configuration Register (DMACFG)......................................................................5-6
5-4 Interrupt Control Unit Configuration..............................................................................5-9
5-5 Interrupt Configuration Register (INTCFG).................................................................5-10
5-6 Timer/Counter Unit Configuration...............................................................................5-12
5-7 Timer Configuration Register (TMRCFG)...................................................................5-13
5-8 Serial I/O Unit 0 Configuration....................................................................................5-15
5-9 Serial I/O Unit 1 Configuration....................................................................................5-16
5-10 SIO and SSIO Configuration Register (SIOCFG).......................................................5-17
5-11 SSIO Unit Configuration .............................................................................................5-18
5-12 Configuration of Chip-select Unit and Clock and Power Management Unit ...............5-20
5-13 Core Configuration .....................................................................................................5-21
5-14 Port 92 Configuration Register (PORT92)..................................................................5-22
5-15 Pin Configuration Register (PINCFG).........................................................................5-24
5-16 Port 1 Configuration Register (P1CFG)......................................................................5-25
5-17 Port 2 Configuration Register (P2CFG)......................................................................5-26
5-18 Port 3 Configuration Register (P3CFG)......................................................................5-27
6-1 Basic External Bus Cycles............................................................................................6-6
6-2 Simplified Bus State Diagram (Does Not Include Address Pipelining or Hold states)..6-8
6-3 Ready Logic ...............................................................................................................6-11
6-4 Basic Internal and External Bus Cycles......................................................................6-12
6-5 Nonpipelined Address Read Cycles ...........................................................................6-15
6-6 Nonpipelined Address Write Cycles ...........................................................................6-18
6-7 Complete Bus States (Including Pipelined Address) ..................................................6-20
6-8 Pipelined Address Cycles...........................................................................................6-21
6-9 Interrupt Acknowledge Cycles ....................................................................................6-25
6-10 Halt Cycle ...................................................................................................................6-27
6-11 Basic Refresh Cycle ...................................................................................................6-29
6-12 Refresh Cycle During HOLD/HLDA............................................................................6-30
6-13 16-bit Cycles to 8-bit Devices (Using BS8#)...............................................................6-33
6-14 LOCK# Signal During Address Pipelining ..................................................................6-35
6-15 Intel386 EX Processor to Intel387 SX Math Coprocessor Interface...........................6-39
xvi
FIGURES
Page