Timer Clock Select Register 2 Format - NEC PD78081(A) User Manual

7 6 5
Symbol
TCL27 TCL26 TCL25
TCL2
TCL22 TCL21 TCL20
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0
1
1 1 0
1 1 1
TCL27 TCL26 TCL25
0
1 0 0
1 0 1
1 1 0
1 1 1
Cautions 1. When rewriting TCL2 to other data, stop the timer operation beforehand.
2. Set 0 to bits 3 and 4.
Remarks 1. f
XX
2. f
X
3.
4. MCS : Oscillation mode selection register (OSMS) bit 0
5. Values in parentheses when operated at f
CHAPTER 9 BUZZER OUTPUT CONTROL CIRCUIT
Figure 9-2. Timer Clock Select Register 2 Format
4 3 2 1
0 0 TCL22 TCL21 TCL20
Watchdog Timer Count Clock Selection
MCS=1
3 3
f /2 f /2 (625 kHz)
XX X
4 4
f /2 f /2 (313 kHz)
XX X
5 5
f /2 f /2 (156 kHz)
XX X
6 6
f /2 f /2 (78.1 kHz)
XX X
7 7
f /2 f /2 (39.1 kHz)
XX X
8 8
f /2 f /2 (19.5 kHz)
XX X
9 9
f /2 f /2 (9.8 kHz)
XX X
11 11
f /2 f /2 (2.4 kHz)
XX X
Buzzer Output Frequency Selection
MCS=1
Buzzer output disable
9 9
f /2 f /2 (9.8 kHz)
XX X
10 10
f /2 f /2 (4.9 kHz)
XX X
11 11
f /2 f /2 (2.4 kHz)
XX X
Setting prohibited
: Main system clock frequency (f
: Main system clock oscillation frequency
: don't care
After
0 Address
Reset
FF42H 00H
or f /2)
X X
= 5.0 MHz
X
R/W
R/W
MCS=0
4
f /2 (313 kHz)
X
5
f /2 (156 kHz)
X
6
f /2 (78.1 kHz)
X
7
f /2 (39.1 kHz)
X
8
f /2 (19.5 kHz)
X
9
f /2 (9.8 kHz)
X
10
f /2 (4.9 kHz)
X
12
f /2 (1.2 kHz)
X
MCS=0
10
f /2 (4.9 kHz)
X
11
f /2 (2.4 kHz)
X
12
f /2 (1.2 kHz)
X
117