Baud Rate Generator Block Diagram - NEC PD78081(A) User Manual

Transmit
Clock
Receive
Clock
Start Bit Detection
138
CHAPTER 11 SERIAL INTERFACE CHANNEL 2
Figure 11-2. Baud Rate Generator Block Diagram
CSIE2
TXE
1/2
MDL0-MDL3
1/2
RXE
Start Bit
Sampling Clock
5-Bit
Counter
Match
Decoder
4
Match
5-Bit
Counter
4
TPS3 TPS2 TPS1 TPS0
Baud Rate Generator
Control Register
ASCK/SCK2/P72
Selector
f
xx
4
TPS0-TPS3
SCK
CSCK
MDL3 MDL2 MDL1 MDL0
Internal Bus
-f /2 10
xx