NEC PD78081(A) User Manual page 247

Instruction
Mnemonic
Group
CALL !addr16
CALLF !addr11
CALLT [addr5]
Call/return
BRK
RET
RETI
RETB
PSW
PUSH
rp
PSW
Stack
POP
manipu-
rp
late
SP, #word
MOVW SP, AX
AX, SP
!addr16
Uncondi-
tional BR $addr16
branch
AX
BC $addr16
BNC $addr16
Conditional
branch
BZ $addr16
BNZ $addr16
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
Remark One instruction clock cycle is one cycle of the CPU clock (f
224
CHAPTER 16 INSTRUCTION SET
Operands Byte
Note 1
3 7
2 5
1 6
1 6
1 6
1 6
1 6
1 2
1 4
1 2
1 4
4 –
2 –
2 –
3 6
2 6
2 8
2 6
2 6
2 6
2 6
Clock
Note 2
(SP – 1) (PC + 3)
–
PC addr16, SP
(SP – 1) (PC + 2)
– PC 00001, PC
15 – 11
SP SP – 2
(SP – 1) (PC + 1)
PC (00000000, addr5 + 1),
H
–
PC (00000000, addr5),
L
SP SP – 2
(SP – 1) PSW, (SP – 2)
– (SP – 3) (PC + 1)
PC (003EH), SP
L
PC (SP + 1), PC
H
–
SP SP + 2
PC (SP + 1), PC
H
– PSW (SP + 2), SP
NMIS 0
PC (SP + 1), PC
H
–
PSW (SP + 2), SP
– (SP – 1) PSW, SP
(SP – 1) rp
H
–
SP SP – 2
– PSW (SP), SP
rp (SP + 1), rp
H
–
SP SP + 2
10 SP word
8 SP AX
8 AX SP
– PC addr16
– PC PC + 2 + jdisp8
– PC A, PC
H L
– PC PC + 2 + jdisp8 if CY = 1
– PC PC + 2 + jdisp8 if CY = 0
– PC PC + 2 + jdisp8 if Z = 1
– PC PC + 2 + jdisp8 if Z = 0
) selected by the PCC register.
CPU
Operation
, (SP – 2) (PC + 3)
H
SP – 2
, (SP – 2) (PC + 2)
H
addr11,
10 – 0
, (SP – 2) (PC + 1)
H
(PC + 1) ,
H
, PC (003FH),
L H
SP – 3, IE 0
(SP),
L
(SP),
L
SP + 3,
(SP),
L
SP + 3
SP – 1
, (SP – 2) rp ,
L
SP + 1
(SP),
L
X
Flag
Z AC CY
,
L
,
L
,
L
R R R
R R R
R R R