NEC PD78081(A) User Manual page 243

Instruction
Mnemonic
Group
A, #byte
saddr, #byte
A, r
r, A
A, saddr
SUB
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
A, #byte
saddr, #byte
A, r
r, A
A, saddr
8-bit
SUBC
operation
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
A, #byte
saddr, #byte
A, r
r, A
A, saddr
AND
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
3. Except "r = A"
Remark One instruction clock cycle is one cycle of the CPU clock (f
220
CHAPTER 16 INSTRUCTION SET
Operands Byte
Note 1
2 4
3 6
Note 3
2 4
2 4
2 4
3 8
1 4
2 8
2 8
2 8
2 4
3 6
Note 3
2 4
2 4
2 4
3 8
1 4
2 8
2 8
2 8
2 4
3 6
Note 3
2 4
2 4
2 4
3 8
1 4
2 8
2 8
2 8
Clock
Note 2
– A, CY A – byte
8 (saddr), CY
– A, CY A – r
– r, CY r – A
5 A, CY A – (saddr)
9 A, CY A – (addr16)
5 A, CY A – (HL)
9 A, CY A – (HL + byte)
9 A, CY A – (HL + B)
9 A, CY A – (HL + C)
– A, CY A – byte – CY
8 (saddr), CY
– A, CY A – r – CY
– r, CY r – A – CY
5 A, CY A – (saddr) – CY
9 A, CY A – (addr16) – CY
5 A, CY A – (HL) – CY
9 A, CY A – (HL + byte) – CY
9 A, CY A – (HL + B) – CY
9 A, CY A – (HL + C) – CY
– A A byte
8 (saddr) (saddr) byte
– A A r
– r r A
5 A A (saddr)
9 A A (addr16)
5 A A (HL)
9 A A (HL + byte)
9 A A (HL + B)
9 A A (HL + C)
) selected by the PCC register.
CPU
Operation
(saddr) – byte
(saddr) – byte – CY
Flag
Z AC CY