Block Diagram - NEC PD78081(A) User Manual

1.7 Block Diagram

8-bit TIMER/
P100/TI5/TO5
EVENT COUNTER 5
8-bit TIMER/
P101/TI6/TO6
EVENT COUNTER 6
SI2/R D/P70
X
SO2/T D/P71
X
SCK2/ASCK/P72
ANI0/P10-
ANI7/P17
AV
DD
AV
SS
AV
REF
INTP1/P01-
INTP3/P03
BUZZER OUTPUT
BUZ/P36
CLOCK OUTPUT
PCL/P35
CONTROL
Remarks 1. The internal ROM and high-speed RAM capacities depend on the product.
2. Pin connection in parentheses is intended for the PD78P083.
CHAPTER 1 OUTLINE
WATCHDOG
TIMER
SERIAL
INTERFACE 2
A/D
CONVERTER
INTERRUPT
CONTROL
78K/0
CPU
ROM
CORE
RAM
V V IC
DD SS
(V )
PP
P00
PORT 0
P01-P03
P10-P17
PORT 1
P30-P37
PORT 3
PORT 5 P50-P57
P70-P72
PORT 7
PORT 10 P100, P101
RESET
SYSTEM
X1
CONTROL
X2
11