NEC PD78081(A) User Manual page 212

Example 1. Example of when a multiple interrupt is generated twice.
Main Processing
EI
INTxx
(PR=1)
Two interrupt requests, INTyy and INTzz, are acknowledged during processing of interrupt INTxx,
and a multiple interrupt is generated. Before each interrupt request is acknowledged, the EI
instruction is always executed and interrupt request acknowledgment enabled.
Example 2. Example of when a multiple interrupt is not generated because of priority control.
Interrupt request INTyy, which has been generated during processing of interrupt INTxx, and which
has an interrupt priority that is lower than that of INTxx, is not acknowledged, and a multiple interrupt
is not generated. Interrupt request INTyy is reserved and is acknowledged after execution of one
main processing instructions.
PR = 0 : High priority level
PR = 1 : Low priority level
IE = 0 : Interrupt request acknowledge disabled
CHAPTER 12 INTERRUPT FUNCTION
Figure 12-14. Multiple Interrupt Example (1/2)
INTxx
Servicing
IE=0
EI
INTyy
(PR=0)
RETI
Main Processing
EI
IE=0
INTyy
INTxx
(PR=1)
(PR=0)
1 Instruction
Execution
INTyy
Servicing
IE=0 IE=0
EI
INTzz
(PR=0)
RETI
INTxx INTyy
Servicing Servicing
EI
RETI
IE=0
RETI
INTzz
Servicing
RETI
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