Clock Generator Control Register; Processor Clock Control Register Format - NEC PD78081(A) User Manual

5.3 Clock Generator Control Register

The clock generator is controlled by the following two registers:
• Processor clock control register (PCC)
• Oscillation mode selection register (OSMS)
(1) Processor clock control register (PCC)
The PCC sets whether to use CPU clock selection and the ratio of division.
The PCC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets the PCC to 04H.
Symbol 7 7 6 6
PCC 0 0
PCC2 PCC1 PCC0
0 0
0 0
0 1
0 1
1 0
Other than above
Caution Set 0 to the bits 3 to 7.
Remarks 1. f
2. f
3. MCS : Bit 0 of oscillation mode selection register (OSMS)
4. Figures in parentheses indicate minimum instruction execution time : 2f
CHAPTER 5 CLOCK GENERATOR
Figure 5-2. Processor Clock Control Register Format
5 4 3 2
0 0 0 PCC2 PCC1 PCC0
CPU CIock Selection (f
MCS=1
0
f f
XX x
1 f /2 f /2 (0.8 s)
XX x
2 2
0 f /2 f /2
XX x
3 3
f /2 f /2
1
XX x
4 4
0
f /2 f /2
XX x
Setting prohibited
: Main system clock frequency (f
XX
: Main system clock oscillator frequency
X
at f = 5.0 MHz.
X
1 0 Address
FFFBH
)
CPU
(0.4 s)
(1.6 s)
(3.2 s)
(6.4 s)
or f /2)
X X
After
Reset R/W
04H R/W
MCS=0
f /2 (0.8 s)
x
2
f /2 (1.6 s)
x
3
f /2 (3.2 s)
x
4
f /2 (6.4 s)
x
5
f /2 (12.8 s)
x
when operating
CPU
71