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NEC PD78081(A) User Manual

8-bit single-chip microcontroller
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8-BIT SINGLE-CHIP MICROCONTROLLER
©
1992
1994
PD78083 SUBSERIES
PD78081
PD78082
PD78P083
PD78P083(A)
PD78P081(A2)
Document No. U12176EJ2V0UM00 (2nd edition)
(O. D. No. IEU-886)
Date Published May 1997 N
Printed in Japan
PD78081(A)
PD78082(A)

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Summary of Contents for NEC NEC PD78081(A)

  • Page 1 PD78083 SUBSERIES 8-BIT SINGLE-CHIP MICROCONTROLLER © 1992 1994 PD78081 PD78081(A) PD78082 PD78082(A) PD78P083 PD78P083(A) PD78P081(A2) Document No. U12176EJ2V0UM00 (2nd edition) (O. D. No. IEU-886) Date Published May 1997 N Printed in Japan...
  • Page 2 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate.
  • Page 3 MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. IBM DOS, PC/AT and PC DOS are trademarks of International Business Machines Corporation. HP9000 Series 300, HP9000 Series 700, and HP-UX are trademarks of Hewlett-Packard Company.
  • Page 4 The application circuits and their parameters are for reference only and are not intended for use in actual design-ins. The information in this document is subject to change without notice. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation.
  • Page 5 Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
  • Page 6 The following Development Tools have been added: IE-78000-R-A, IE-70000-98-IF-B, IE-70000-98N-IF, IE-70000-PC-IF-B, IE-78000-R-SV3, SM78K0, ID78K0 p. 239 A.4 OS for IBM PC has been added. p. 240 Table A-2. System-Up Method from Other In-Circuit Emulator to IE-78000-R-A has been added. p. 244 B.1 Real-time OS has been added.
  • Page 7 Readers This manual has been prepared for user engineers who want to understand the functions of the systems and programs. Caution In the PD78083 Subseries, the PD78P083DU is not designed to maintain the reliability required for use in customers’ mass-produced equipment. Please use this device only for experimentation or for evaluation of functions.
  • Page 8 Legend Data representation weight Active low representations Note Caution Remarks Numeral representations Examples of use in this manual are prepared for “Standard” quality level devices for general electronic equipment. In the case of examples of use in this manual for devices which meet “Special” quality level requirements, please use each device only after studying each part that is actuall to be used, the circuitry and the quality level of each component before use.
  • Page 9 Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Related documents for PD78054 subseries PD78083 Subseries User’s Manual PD78081, 78082 Data Sheet PD78P083 Data Sheet PD78081(A), 78082(A), 78081(A2) Data Sheet PD78P083(A) Data Sheet PD78083 Subseries Special Function Register Table 78K/0 Series User’s Manual—Instruction...
  • Page 10 CC78K Series C Compiler CC78K/0 C Compiler CC78K/0 C Compiler Application Note CC78K Series Library Source File PG-1500 PROM Programmer PG-1500 Controller PC-9800 Series (MS-DOS™) Base PG-1500 Controller IBM PC Series (PC DOS™) Base IE-78000-R IE-78000-R-A IE-78000-R-BK IE-78078-R-EM EP-78083 SM78K0 System Simulator Windows™ Base...
  • Page 11 Documents for Embedded Software (User’s Manual) Document name 78K/0 Series Real-Time OS OS for 78K/0 Series MX78K0 Fuzzy Knowledge Data Creation Tool 78K/0, 78K/II, 87AD Series Fuzzy Inference Development Support System—Translator 78K/0 Series Fuzzy Inference Development Support System—Fuzzy Inference Module 78K/0 Series Fuzzy Inference Development Support System—Fuzzy Inference Debugger Other Documents Document name...

  • Page 12: Table Of Contents

    CHAPTER 1 OUTLINE ... Features ... Applications ... Ordering Information ... Quality Grade ... Pin Configuration (Top View) ... 78K/0 Series Development ... Block Diagram ... Outline of Function ... Differences between the PD78081, 78082 and 78P083, the PD78081(A), 78082(A) and 78P083(A), and the PD78081(A2) ...
  • Page 13 3.2.3 Special Function Register (SFR) ... Instruction Address Addressing ... 3.3.1 Relative Addressing ... 3.3.2 Immediate addressing ... 3.3.3 Table indirect addressing ... 3.3.4 Register addressing ... Operand Address Addressing ... 3.4.1 Implied addressing ... 3.4.2 Register addressing ... 3.4.3 Direct addressing ...
  • Page 14 8-Bit Timer/Event Counters 5 and 6 Operations ... 6.4.1 Interval timer operations ... 6.4.2 External event counter operation ... 6.4.3 Square-wave output ... 6.4.4 PWM output operations ... Cautions on 8-Bit Timer/Event Counters 5 and 6 ... CHAPTER 7 WATCHDOG TIMER ... Watchdog Timer Functions ...
  • Page 15 Language Processing Software ... PROM Programming Tools ... A.2.1 Hardware ... A.2.2 Software ... Debugging Tools ... A.3.1 Hardware ... A.3.2 Software (1/3) ... A.3.2 Software (2/3) ... A.3.2 Software (3/3) ... OS for IBM PC ... – iv –...
  • Page 16 System-Upgrade Method from Other In-Circuit Emulators to 78K/0 Series In-Circuit Emulator... APPENDIX B EMBEDDED SOFTWARE ... Real-time OS ... Fuzzy Inference Development Support System ... APPENDIX C REGISTER INDEX ... C.1 Register Index ... APPENDIX D REVISION HISTORY ... – v –...
  • Page 17 Fig. No. Pin Input/Output Circuit of List ... Memory Map ( PD78081) ... Memory Map ( PD78082) ... Memory Map ( PD78P083) ... Data Memory Addressing ( PD78081) ... Data Memory Addressing ( PD78082) ... Data Memory Addressing ( PD78P083) ... Program Counter Configuration ...
  • Page 18 Fig. No. 6-10 8-Bit Timer Mode Control Register Setting for External Event Counter Operation ... 6-11 External Event Counter Operation Timings (with Rising Edge Specification) ... 6-12 8-Bit Timer Mode Control Register Settings for Square-Wave Output Operation ... 6-13 8-Bit Timer Mode Control Register Settings for PWM Output Operation ... 6-14 PWM Output Operation Timing (Active high setting) ...
  • Page 19 Fig. No. 11-6 Baud Rate Generator Control Register Format (2/2) ... 11-7 Asynchronous Serial Interface Transmit/Receive Data Format ... 11-8 Asynchronous Serial Interface Transmission Completion Interrupt Request Timing ... 11-9 Asynchronous Serial Interface Reception Completion Interrupt Request Timing ... 11-10 Receive Error Timing ...
  • Page 20 Fig. No. 15-6 PROM Read Timing ... Development Tool Configuration ... EV-9200G-44 Drawing (For Reference Only) ... EV-9200G-44 Footprint (For Reference Only) ... FIGURE (4/4) Title – ix – Page...
  • Page 21 Table. No. Differences between the PD78081, 78082 and 78P083, the PD78081(A), 78082(A) and 78P083(A), and the PD78081(A2) ... Type of Input/Output Circuit of Each Pin ... Vector Table ... Special-Function Register List (1/2) ... Special-Function Register List (2/2) ... Port Functions ... Port Configuration ...
  • Page 22 Table. No. 12-1 Interrupt Source List ... 12-2 Various Flags Corresponding to Interrupt Request Sources ... 12-3 Times from Maskable Interrupt Request Generation to Interrupt Service ... 12-4 Interrupt Request Enabled for Multiple Interrupt during Interrupt Servicing ... 13-1 HALT Mode Operating Status ... 13-2 Operation after HALT Mode Release ...
  • Page 23 [MEMO] – xii –...

  • Page 24: Chapter 1 Outline

    1.1 Features On-chip ROM and RAM Part Number PD78081 PD78082 PD78P083 Note The capacities of internal PROM and internal high-speed RAM can be changed by means of the memory size switching register (IMS). Instruction execution time changeable from high speed (0.4 s: In main system clock 5.0 MHz operation) to low speed (12.8 s: In main system clock 5.0 MHz operation) Instruction set suited to system control •...

  • Page 25: Applications

    1.2 Applications PD78081, 78082, 78P083: Airbags, CRT displays, keyboards, air conditioners, hot water dispensers, boilers, fan heaters, dashboards, etc. PD78081(A), 78082(A), 78P083(A), 78081(A2): Automobile electrical control devices, gas detector cutoff devices, various safety devices, etc. 1.3 Ordering Information Part number PD78081CU- 42-pin plastic shrink DIP (600 mil) PD78081GB-...

  • Page 26: Quality Grade

    1.4 Quality Grade Part number PD78081CU- 42-pin plastic shrink DIP (600 mil) PD78081GB- -3B4 44-pin plastic QFP (10 PD78081GB- -3BS-MTX 44-pin plastic QFP (10 PD78082CU- 42-pin plastic shrink DIP (600 mil) PD78082GB- -3B4 44-pin plastic QFP (10 PD78082GB- -3BS-MTX 44-pin plastic QFP (10 PD78P083CU 42-pin plastic shrink DIP (600 mil) PD78P083DU...

  • Page 27: Pin Configuration (Top View)

    1.5 Pin Configuration (Top View) (1) Normal operating mode 42-pin plastic shrink DIP (600 mil) PD78081CU- , 78082CU- 42-pin ceramic shrink DIP (with window) (600 mil) PD78P083DU P35/PCL P36/BUZ P01/INTP1 P02/INTP2 P03/INTP3 RESET IC (V Cautions 1. Be sure to connect IC (Internally Connected) pin to V 2.
  • Page 28 • 44-pin plastic QFP (10 10 mm) PD78081GB- -3B4, 78081GB- PD78082GB- -3B4, 78082GB- PD78P083GB-3B4, 78P083GB-3BS-MTX PD78081GB(A)- -3B4, 78082GB(A)- PD78P083GB(A)-3B4, 78P083GB(A)-3BS-MTX PD78P081GB(A2)- -3B4 P12/ANI2 P13/ANI3 P14/ANI4 P15/ANI5 P16/ANI6 P17/ANI7 P72/ASCK/SCK2 P71/TxD/SO2 P70/RxD/SI2 P101/TI6/TO6 P100/TI5/TO6 Note Under development Cautions 1. Be sure to connect IC (Internally Connected) pin to V 2.
  • Page 29 Pin Identifications ANI0 to ANI7 Analog Input ASCK Asynchronous Serial Clock Analog Power Supply Analog Reference Voltage Analog Ground Buzzer Clock Internally Connected INTP1 to INTP3 Interrupt from Peripherals Non-connection P00 to P03 Port 0 P10 to P17 Port 1 P30 to P37 Port 3 P50 to P57...
  • Page 30 (2) PROM programming mode • 42-pin plastic shrink DIP (600 mil) PD78P083CU, 78P083CU(A) • 42-pin ceramic shrink DIP (with window) (600 mil) PD78P083DU RESET Open Cautions 1. (L) : Individually connect to V 2. V : Connect to the ground. 3.
  • Page 31 • 44-pin plastic QFP (10 PD78P083GB-3B4, 78P083GB-3BS-MTX PD78P083GB(A)-3B4, 78P083GB(A)-3BS-MTX Note Under development Cautions 1. (L) : Connect individually to V 2. V : Connect to the ground. 3. RESET : Set to the low level. 4. Open : Do not connect anything. A0 to A14 : Address Bus : Chip Enable...

  • Page 32: Series Development

    1.6 78K/0 Series Development The following shows the 78K/0 Series products development. Subseries names are shown inside frames. Control 100-pin µPD78075B 100-pin µPD78078 100-pin µPD78070A 100-pin µPD780018 80-pin µPD780058 80-pin µPD78058F 80-pin µPD78054 64-pin µPD780034 64-pin µPD780024 64-pin µPD78014H 64-pin µPD78018F 64-pin µPD78014...
  • Page 33 The following table shows the differences among subseries functions. Function Subseries name capacity Control PD78075B 32K to 40K 4 ch 1 ch 1 ch 1 ch 8 ch PD78078 48K to 60K PD78070A — PD780018 48K to 60K PD780058 24K to 60K 2 ch PD78058F 48K to 60K PD78054...

  • Page 34: Block Diagram

    1.7 Block Diagram 8-bit TIMER/ P100/TI5/TO5 EVENT COUNTER 5 8-bit TIMER/ P101/TI6/TO6 EVENT COUNTER 6 WATCHDOG TIMER SI2/R D/P70 SERIAL SO2/T D/P71 INTERFACE 2 SCK2/ASCK/P72 ANI0/P10- ANI7/P17 CONVERTER INTP1/P01- INTERRUPT INTP3/P03 CONTROL BUZZER OUTPUT BUZ/P36 CLOCK OUTPUT PCL/P35 CONTROL Remarks 1. The internal ROM and high-speed RAM capacities depend on the product. 2.

  • Page 35: Outline Of Function

    1.8 Outline of Function Part Number Item Internal memory High-speed RAM Memory space General register Instruction cycle Instruction set I/O ports A/D converter Serial interface Timer Timer output Clock output Buzzer output Vectored Maskable interrupt Non-maskable source Software Supply voltage Operating ambient temperature Package Note...

  • Page 36: Differences Between The Pd78081, 78082 And 78P083, The Pd78081(A), 78082(A) And 78P083(A), And The Pd78081(A2)

    Differences between the 78P083(A), and the PD78081(A2) Table 1-1 Differences between the PD78081, 78082 and 78P083, the PD78081(A), 78082(A) and Part Number Item Quality grade Standard Supply voltage = 1.8 to 5.5 V Operating ambient temperature = –40 to +85 C Electrical specifications Please refer to the individual data sheets.
  • Page 37 CHAPTER 1 OUTLINE [MEMO]...

  • Page 38: Chapter 2 Pin Function

    2.1 Pin Function List 2.1.1 Normal operating mode pins (1) Port pins Pin Name Input/Output Input Input/output P10-P17 Input/output P30-P34 Input/output P50-P57 Input/output Input/output P100 Input/output P101 Note When P10/ANI0-P17/ANI7 pins are used as the analog inputs for the A/D converter, set the port 1 to the input mode.

  • Page 39: Prom Programming Mode Pins ( Pd78P083 Only)

    (2) Pins other than port pins Pin Name Input/Output INTP1 Input External interrupt request input by which the active edge INTP2 (rising edge, falling edge, or both rising and falling edges) INTP3 can be specified. Input Serial interface serial data input. Output Serial interface serial data output.

  • Page 40: Description Of Pin Functions

    2.2 Description of Pin Functions 2.2.1 P00 to P03 (Port 0) These are 4-bit input/output ports. Besides serving as input/output ports, they function as an external interrupt request input. The following operating modes can be specified bit-wise. (1) Port mode P00 functions as input-only port and P01 to P03 function as input/output ports.

  • Page 41: P30 To P37 (Port 3)

    2.2.3 P30 to P37 (Port 3) These are 8-bit input/output ports. Beside serving as input/output ports, they function as clock output and buzzer output. The following operating modes can be specified bit-wise. (1) Port mode These ports function as 8-bit input/output ports. They can be specified bit-wise as input or output ports with port mode register 3 (PM3).

  • Page 42: P70 To P72 (Port 7)

    2.2.5 P70 to P72 (Port 7) This is a 3-bit input/output port. In addition to its use as an input/output port, it also has serial interface data input/ output and clock input/output functions. The following operating modes can be specified bit-wise. (1) Port mode Port 7 functions as a 3-bit input/output port.

  • Page 43: Av Ref

    2.2.7 AV A/D converter reference voltage input pin. When A/D converter is not used, connect this pin to V 2.2.8 AV Analog power supply pin of A/D converter. Always use the same voltage as that of the V converter is not used. 2.2.9 AV This is a ground voltage pin of A/D converter.

  • Page 44: Ic (Mask Rom Version Only)

    2.2.15 IC (Mask ROM version only) The IC (Internally Connected) pin is provided to set the test mode to check the PD78083 Subseries at delivery. Connect it directly to the V with the shortest possible wire in the normal operating mode. When a voltage difference is produced between the IC pin and V is too long or an external noise is input to the IC pin, the user's program may not run normally.

  • Page 45: Pin Input/Output Circuits And Recommended Connection Of Unused Pins

    Pin Input/Output Circuits and Recommended Connection of Unused Pins Types of input/output circuits of the pins and recommeded connection of unused pins are shown in Table 2-1. For the configuration of each type of input/output circuit, see Figure 2-1. Table 2-1. Type of Input/Output Circuit of Each Pin Pin Name P01/INTP1 P02/INTP2...

  • Page 46: Pin Input/Output Circuit Of List

    Figure 2-1. Pin Input/Output Circuit of List Type 2 Schmitt-Triggered Input with Hysteresis Characteristics Type 5-A pull-up enable data P-ch output N-ch disable input enable CHAPTER 2 PIN FUNCTION Type 8-A pull-up enable data output disable Type 11 pull-up enable P-ch data output...
  • Page 47 CHAPTER 2 PIN FUNCTION [MEMO]...

  • Page 48: Chapter 3 Cpu Architecture

    3.1 Memory Spaces Figures 3-1 to 3-3 shows memory maps. FFFFH F F 0 0 H FEFFH FEE0H FEDFH FE00H Data memory FDFFH space 2 0 0 0 H 1FFFH Program memory space 0 0 0 0 H CHAPTER 3 CPU ARCHITECTURE CHAPTER 3 CPU ARCHITECTURE Figure 3-1.

  • Page 49: Memory Map ( Pd78082)

    FFFFH F F 0 0 H FEFFH FEE0H FEDFH FD80H Data memory FD7FH space 4 0 0 0 H 3FFFH Program memory space 0 0 0 0 H CHAPTER 3 CPU ARCHITECTURE Figure 3-2. Memory Map ( PD78082) Special Function Registers (SFRs) 8 bits General Registers...

  • Page 50: Memory Map ( Pd78P083)

    FFFFH F F 0 0 H FEFFH General Registers FEE0H FEDFH FD00H Data memory FCFFH space 6 0 0 0 H 5FFFH Program memory space 0 0 0 0 H CHAPTER 3 CPU ARCHITECTURE Figure 3-3. Memory Map ( PD78P083) Special Function Registers (SFRs) 8 bits...

  • Page 51: Internal Program Memory Space

    3.1.1 Internal program memory space The internal program memory is mask ROM with a 8192 8-bit configuration in the PD78082, and PROM with a 24576 The internal program memory space stores programs and table data. Normally, they are addressed with a program counter (PC).

  • Page 52: Internal Data Memory Space

    3.1.2 Internal data memory space The internal high speed RAM configuration is 256 8-bit in the PD8P083. In this area, four banks of general registers, each bank consisting of eight 8-bit registers, are allocated in the 32-byte area FEE0H to FEFFH. The internal high-speed RAM can also be used as a stack memory area.

  • Page 53: Data Memory Addressing ( Pd78081)

    Figure 3-4. Data Memory Addressing ( PD78081) FFFFH Special Function Registers (SFRs) 8 bits F F 2 0 H FF1FH F F 0 0 H FEFFH General Registers 8 bits FEE0H FEDFH Internal High-speed RAM 8 bits FE20H FE1FH FE00H FDFFH Unusable 2 0 0 0 H...

  • Page 54: Data Memory Addressing ( Pd78082)

    Figure 3-5. Data Memory Addressing ( PD78082) FFFFH Special Function Registers (SFRs) 8 bits F F 2 0 H FF1FH F F 0 0 H FEFFH General Registers 8 bits FEE0H FEDFH Internal High-speed RAM 8 bits FE20H FE1FH FD80H FD7FH Unusable 4 0 0 0 H...

  • Page 55: Data Memory Addressing ( Pd78P083)

    Figure 3-6. Data Memory Addressing ( PD78P083) FFFFH Special Function Registers (SFRs) 8 bits F F 2 0 H FF1FH F F 0 0 H FEFFH General Registers 8 bits FEE0H FEDFH Internal High-speed RAM 8 bits FE20H FE1FH FD00H FCFFH Unusable 6 0 0 0 H...

  • Page 56: Processor Registers

    3.2 Processor Registers The PD78083 subseries units incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter, a program status word and a stack pointer. (1) Program counter (PC) The program counter is a 16-bit register which holds the address information of the next program to be executed.
  • Page 57 (a) Interrupt enable flag (IE) This flag controls the interrupt request acknowledge operations of the CPU. When IE = 0, all interrupts except the non-maskable interrupt are disabled (DI status). When IE = 1, interrupts are enabled (EI status). At this time, acknowledgment of interrupts is controlled with an inservice priority flag (ISP), an interrupt mask flag for various interrupt sources, and a priority specify flag.

  • Page 58: Stack Pointer Configuration

    (3) Stack pointer (SP) This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM area (FE00H-FEFFH for the PD78P083) can be set as the stack area. The SP is decremented ahead of write (save) to the stack memory and is incremented after read (reset) from the stack memory.

  • Page 59: General Registers

    3.2.2 General registers A general register is mapped at particular addresses (FEE0H to FEFFH) of the data memory. It consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L and H). Each register can also be used as an 8-bit register. Two 8-bit registers can be used in pairs as a 16-bit register (AX, BC, DE and HL).

  • Page 60: Special Function Register (Sfr)

    3.2.3 Special Function Register (SFR) Unlike a general register, each special-function register has special functions. It is allocated in the FF00H to FFFFH area. The special-function register can be manipulated like the general register, with the operation, transfer and bit manipulation instructions.

  • Page 61: Special-Function Register List (1/2)

    Table 3-2. Special-Function Register List (1/2) Address Special-Function Register (SFR) Name FF00H Port0 FF01H Port1 FF03H Port3 FF05H Port5 FF07H Port7 FF0AH Port10 FF1FH A/D conversion result register FF20H Port mode register 0 FF21H Port mode register 1 FF23H Port mode register 3 FF25H Port mode register 5 FF27H...

  • Page 62: Special-Function Register List (2/2)

    Table 3-2. Special-Function Register List (2/2) Address Special-Function Register (SFR) Name FFEAH Priority order specify flag register 1L FFECH External interrupt mode register 0 FFEDH External interrupt mode register 1 FFF0H Memory size switching register FFF2H Oscillation mode selection register FFF3H Pull-up resistor option register H FFF7H...

  • Page 63: Instruction Address Addressing

    3.3 Instruction Address Addressing An instruction address is determined by program counter (PC) contents. The contents of PC are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. When a branch instruction is executed, the branch destination information is set to the PC and branched by the following addressing.

  • Page 64: Immediate Addressing

    3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. The CALL !addr16 and BR !addr16 instruction can branch in the entire memory space. The CALLF !addr11 instruction branches to an area of addresses 0800H through 0FFFH.

  • Page 65: Table Indirect Addressing

    3.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (PC) and branched. Before the CALLT [addr5] instruction is executed, table indirect addressing is performed. This instruction references an address stored in the memory table at addresses 40H through 7FH, and can branch in the entire memory space.

  • Page 66: Register Addressing

    3.3.4 Register addressing [Function] Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the BR AX instruction is executed. [Illustration] CHAPTER 3 CPU ARCHITECTURE...

  • Page 67: Operand Address Addressing

    3.4 Operand Address Addressing The following various methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 3.4.1 Implied addressing [Function] The register which functions as an accumulator (A and AX) in the general register is automatically (illicitly) addressed.

  • Page 68: Register Addressing

    3.4.2 Register addressing [Function] This addressing accesses a general register as an operand. The general register accessed is specified by the register bank select flags (RBS0 and RBS1) and register specify code (Rn or RPn) in an instruction code. Register addressing is carried out when an instruction with the following operand format is executed. When an 8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code.

  • Page 69: Direct Addressing

    3.4.3 Direct addressing [Function] This addressing directly addresses the memory indicated by the immediate data in an instruction word. [Operand format] [Description example] MOV A, !0FE00H; when setting !addr16 to FE00H Operation code [Illustration] CHAPTER 3 CPU ARCHITECTURE Identifier Description addr16 Label or 16-bit immediate data 1 0 0 0 1 1 1 0...

  • Page 70: Short Direct Addressing

    3.4.4 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. The fixed space to which this address is applied is a 256-byte space of addresses FE20H through FF1FH. An internal high-speed RAM and a special-function register (SFR) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.
  • Page 71 [Description example] MOV 0FE30H, #50H; when setting saddr to FE30H and immediate data to 50H Operation code [Illustration] OP code saddr-offset Effective Address When 8-bit immediate data is 20H to FFH, When 8-bit immediate data is 00H to 1FH, CHAPTER 3 CPU ARCHITECTURE 0 0 0 1 0 0 0 1 0 0 1 1 0 0 0 0 0 1 0 1 0 0 0 0...

  • Page 72: Special-Function Register (Sfr) Addressing

    3.4.5 Special-Function Register (SFR) addressing [Function] The memory-mapped special-function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFR mapped at FF00H to FF1FH can be accessed with short direct addressing. [Operand format] Identifier Special-function register name...

  • Page 73: Register Indirect Addressing

    3.4.6 Register indirect addressing [Function] This addressing addresses the memory with the contents of a register pair specified as an operand. The register pair to be accessed is specified by the register bank select flags (RBS0 and RBS1) and register pair specify code in an instruction code.

  • Page 74: Based Addressing

    3.4.7 Based addressing [Function] This addressing addresses the memory by adding 8-bit immediate data to the contents of the HL register pair which is used as a base register and by using the result of the addition. The HL register pair to be accessed is in the register bank specified by the register bank select flags (RBS0 and RBS1).

  • Page 75: Based Indexed Addressing

    3.4.8 Based indexed addressing [Function] This addressing addresses the memory by adding the contents of the HL register, which is used as a base register, to the contents of the B or C register specified in the instruction word, and by using the result of the addition. The HL, B, and C registers to be accessed are registers in the register bank specified by the register bank select flags (RBS0 and RBS1).

  • Page 76: Chapter 4 Port Functions

    4.1 Port Functions The PD78083 Subseries units incorporate an input port and thirty-two input/output ports. Figure 4-1 shows the port configuration. Every port is capable of 1-bit and 8-bit manipulations and can carry out considerably varied control operations. Besides port functions, the ports can also serve as on-chip hardware input/output pins. Port 5 Port 7 Port 10...

  • Page 77: Port Functions

    Pin Name Input/Output Input Port 0 Input/output 4-bit input/output port P10-P17 Input/output Port 1 8-bit input/output port Input/output is specifiable bit-wise. When used as the input port, it is possible to connect a pull-up resistor by software. P30-P34 Input/output Port 3 8-bit input/output port Input/output is specifiable bit-wise.

  • Page 78: Port Configuration

    4.2 Port Configuration A port consists of the following hardware: Item Control register Port Pull-up resistor 4.2.1 Port 0 Port 0 is an 4-bit input/output port with output latch. P01 to P03 pins can specify the input mode/output mode in 1-bit units with the port mode register 0 (PM0).

  • Page 79: P00 Block Diagram

    PUO0 PORT Output Latch (P01 to P03) PM01-PM03 PUO : Pull-up resistor option register PM : Port mode register : Port 0 read signal WR : Port 0 write signal CHAPTER 4 PORT FUNCTIONS Figure 4-2. P00 Block Diagram Figure 4-3. P01 to P03 Block Diagram Selector P-ch P01/INTP1...

  • Page 80: Port 1

    4.2.2 Port 1 Port 1 is an 8-bit input/output port with output latch. It can specify the input mode/output mode in 1-bit units with a port mode register 1 (PM1). When P10 to P17 pins are used as input ports, an on-chip pull-up resistor can be used to them in 8-bit units with a pull-up resistor option register L (PUOL).

  • Page 81: Port

    4.2.3 Port 3 Port 3 is an 8-bit input/output port with output latch. P30 to P37 pins can specify the input mode/output mode in 1-bit units with the port mode register 3 (PM3). When P30 to P37 pins are used as input ports, an on-chip pull-up resistor can be used to them in 8-bit units with a pull-up resistor option register L (PUOL).

  • Page 82: Port

    4.2.4 Port 5 Port 5 is an 8-bit input/output port with output latch. P50 to P57 pins can specify the input mode/output mode in 1-bit units with the port mode register 5 (PM5). When P50 to P57 pins are used as input ports, an on-chip pull-up resistor can be used to them in 8-bit units with a pull-up resistor option register L (PUOL).

  • Page 83: Port

    4.2.5 Port 7 This is a 3-bit input/output port with output latches. Input mode/output mode can be specified bit-wise by means of port mode register 7 (PM7). When pins P70 to P72 are used as input port pins, an on-chip pull-up resistor can be used as a 3-bit unit by means of pull-up resistor option register L (PUOL).

  • Page 84: P71 And P72 Block Diagram

    CHAPTER 4 PORT FUNCTIONS Figure 4-8. P71 and P72 Block Diagram PUO7 PORT Output Latch (P71 and P72) PM71, PM72 Alternate Function PUO : Pull-up resistor option register PM : Port mode register : Port 7 read signal WR : Port 7 write signal Selector P-ch P71/SO2/TxD,...

  • Page 85: Port

    4.2.6 Port 10 This is an 2-bit input/output port with output latches. Input mode/output mode can be specified bit-wise by means of port mode register 10 (PM10). When pins P100 to P101 are used as input port pins, an on-chip pull-up resistor can be used as an 2-bit unit by means of pull-up resistor option register H (PUOH).

  • Page 86: Port Function Control Registers

    4.3 Port Function Control Registers The following two types of registers control the ports. • Port mode registers (PM0, PM1, PM3, PM5, PM7, PM10) • Pull-up resistor option register (PUOH, PUOL) (1) Port mode registers (PM0, PM1, PM3, PM5, PM7, PM10) These registers are used to set port input/output in 1-bit units.

  • Page 87: Port Mode Register And Output Latch Settings When Using Dual-Fucntions

    Table 4-3. Port Mode Register and Output Latch Settings when Using Dual-Functions Pin Name P01 to P03 P10 to P17 P100 P101 Note If a read instruction is performed to these pins when they are used as an alternate function, read data is to be undefined.

  • Page 88: Port Mode Register Format

    Figure 4-10. Port Mode Register Format Symbol PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30 PM57 PM56 PM55 PM54 PM53 PM52 PM51 PM50 PM10 Caution Set 1 to the bits 0, 4 to 7 of PM0, bits 3 to 7 of PM7 and bits 2 to 7 of PM10. CHAPTER 4 PORT FUNCTIONS Address PM03 PM02 PM01...

  • Page 89: Pull-Up Resistor Option Register Format

    (2) Pull-up resistor option register (PUOH, PUOL) This register is used to set whether to use an internal pull-up resistor at each port or not. A pull-up resistor is internally used at bits which are set to the input mode at a port where on-chip pull-up resistor use has been specified with PUOH, PUOL.

  • Page 90: Port Function Operations

    4.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 4.4.1 Writing to input/output port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin.
  • Page 91 CHAPTER 4 PORT FUNCTIONS [MEMO]...

  • Page 92: Chapter 5 Clock Generator

    5.1 Clock Generator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following type of system clock oscillator is available. Main system clock oscillator This circuit oscillates at frequencies of 1 to 5.0 MHz. Oscillation can be stopped by executing the STOP instruction. 5.2 Clock Generator Configuration The clock generator consists of the following hardware.

  • Page 93: Block Diagram Of Clock Generator

    Figure 5-1. Block Diagram of Clock Generator Main System Clock Scaler Oscillator STOP CHAPTER 5 CLOCK GENERATOR Prescaler PCC2 PCC1 Oscillation Mode Selection Register Internal Bus Prescaler Clock to Peripheral Hardware Standby CPU Clock Control Circuit PCC0 Processor Clock Control Register...

  • Page 94: Clock Generator Control Register

    5.3 Clock Generator Control Register The clock generator is controlled by the following two registers: • Processor clock control register (PCC) • Oscillation mode selection register (OSMS) (1) Processor clock control register (PCC) The PCC sets whether to use CPU clock selection and the ratio of division. The PCC is set with a 1-bit or 8-bit memory manipulation instruction.

  • Page 95: Oscillation Mode Selection Register Format

    (2) Oscillation mode selection register (OSMS) This register specifies whether the clock output from the main system clock oscillator without passing through the scaler is used as the main system clock, or the clock output via the scaler is used as the main system clock.

  • Page 96: System Clock Oscillator

    5.4 System Clock Oscillator 5.4.1 Main system clock oscillator The main system clock oscillator oscillates with a crystal resonator or a ceramic resonator (standard: 5.0 MHz) connected to the X1 and X2 pins. External clocks can be input to the main system clock oscillator. In this case, input a clock signal to the X1 pin and an antiphase clock signal to the X2 pin.

  • Page 97: Examples Of Oscillator With Bad Connection (1/2)

    Figure 5-6. Examples of Oscillator with Bad Connection (1/2) (a) Wiring of connection circuits is too long (c) Changing high current is too near a signal conductor CHAPTER 5 CLOCK GENERATOR (b) Signal conductors intersect with each other (d) Current flows through the grounding line of the ocsillator (potential at points A, B, and C fluctuate) High...

  • Page 98: Scaler

    CHAPTER 5 CLOCK GENERATOR Figure 5-6. Examples of Oscillator with Bad Connection (2/2) (c) Signals are fetched 5.4.2 Scaler The scaler divides the main system clock oscillator output (f ) and generates various clocks.

  • Page 99: Clock Generator Operations

    5.5 Clock Generator Operations The clock generator generates the following various types of clocks and controls the CPU operating mode including the standby mode. • Main system clock • CPU clock • Clock to peripheral hardware The following clock generator functions and operations are determined with the processor clock control register (PCC) and the oscillation mode selection register (OSMS).

  • Page 100: Changing Cpu Clock Settings

    5.6 Changing CPU Clock Settings 5.6.1 Time required for CPU clock switchover The CPU clock can be switched over by means of bits 0 to 2 (PCC0 to PCC2) of the processor clock control register (PCC). The actual switchover operation is not performed directly after writing to the PCC, but operation continues on the pre-switchover clock for several instructions (see Table 5-2).

  • Page 101: Cpu Clock Switching Procedure

    5.6.2 CPU clock switching procedure This section describes CPU clock switching procedure. RESET CPU Clock (1) The CPU is reset by setting the RESET signal to low level after power-on. After that, when reset is released by setting the RESET signal to high level, main system clock starts oscillation. At this time, oscillation ) is secured automatically.

  • Page 102: Chapter 6 8-Bit Timer/Event Counters 5 And 6

    CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 The timers incorporated into the PD78083 subseries are outlined below. (1) 8-bit timers/event counters 5 and 6 (TM5 and TM6) This can be used to serve as an interval timer, an external event counter, square wave output with any selected frequency PWM, etc.

  • Page 103: 8-Bit Timer/Event Counters 5 And 6 Functions

    CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 6.1 8-Bit Timer/Event Counters 5 and 6 Functions The 8-bit timer/event counters 5 and 6 (TM5 and TM6) have the following functions. • Interval timer • External event counter • Square-wave output •...

  • Page 104: 8-Bit Timer/Event Counters 5 And 6 Square-Wave Output Ranges

    CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 (2) External event counter The number of pulses of an externally input signal can be measured. (3) Square-wave output A square wave with any selected frequency can be output. Table 6-3. 8-Bit Timer/Event Counters 5 and 6 Square-Wave Output Ranges Minimum pulse width MCS = 1 MCS = 0...

  • Page 105: 8-Bit Timer/Event Counters 5 And 6 Configurations

    CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 6.2 8-Bit Timer/Event Counters 5 and 6 Configurations The 8-bit timer/event counters 5 and 6 consist of the following hardware. Table 6-4. 8-Bit Timer/Event Counters 5 and 6 Configurations Item Timer register Register Timer output Control register...

  • Page 106: Block Diagram Of 8-Bit Timer/Event Counters 5 And 6 Output Control Circuit

    CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 Figure 6-2. Block Diagram of 8-Bit Timer/Event Counters 5 and 6 Output Control Circuit RESET LVRn LVSn TMCn1 TMCn6 INTTMn PWM Output Circuit Timer Output F/F2 TCEn INTTMn OVFn Note PM100 : Bit 0 of port mode register 10 (PM10) PM101 : Bit 1 of PM10 Remarks 1.

  • Page 107: 8-Bit Timer/Event Counters 5 And 6 Control Registers

    CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 (1) Compare registers 50 and 60 (CR50, CR60) These are 8-bit registers to compare the value set to CR50 to the 8-bit timer register 5 (TM5) count value, and the value set to CR60 to the 8-bit timer register 6 (TM6) count value, and, if they match, generate an interrupt request (INTTM5 and INTTM6, respectively).

  • Page 108: Timer Clock Select Register 5 Format

    CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 Figure 6-3. Timer Clock Select Register 5 Format Symbol TCL5 TCL53 TCL52 TCL51 TCL50 Other than above Note The timer output (PWM output) cannot be used in cases where the clock is being input from an external source.

  • Page 109: Timer Clock Select Register 6 Format

    CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 (2) Timer clock select register 6 (TCL6) This register sets count clocks of 8-bit timer register 6. TCL6 is set with an 8-bit memory manipulation instruction. RESET input sets TCL6 to 00H. Figure 6-4.

  • Page 110: 8-Bit Timer Mode Control Register 5 Format

    CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 (3) 8-bit timer mode control register 5 (TMC5) This register enables/stops operation of 8-bit timer register 5, sets the operating mode of 8-bit timer register 5 and controls operation of 8-bit timer/event counter 5 output control circuit. It sets R-S type flip-flop (timer output F/F 1,2) setting/resetting, the active level in PWM mode, inversion enabling/disabling in modes other than PWM mode and 8-bit timer/event counter 5 timer output enabling/ disabling.

  • Page 111: 8-Bit Timer Mode Control Register 6 Format

    CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 (4) 8-bit timer mode control register 6 (TMC6) This register enables/stops operation of 8-bit timer register 6, sets the operating mode of 8-bit timer register 6 and controls operation of 8-bit timer/event counter 6 output control circuit. It sets R-S type flip-flop (timer output F/F 1,2) setting/resetting, active level in PWM mode, inversion enabling/ disabling in modes other than PWM mode and 8-bit timer/event counter 6 timer output enabling/disabling.

  • Page 112: Port Mode Register 10 Format

    CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 (5) Port mode register 10 (PM10) This register sets port 10 input/output in 1-bit units. When using the P100/TI5/TO5 and P101/TI6/TO6 pins for timer output, set PM100, PM101, and output latches of P100 and P101 to 0. PM10 is set with a 1-bit or 8-bit memory manipulation instruction.

  • Page 113: 8-Bit Timer/Event Counters 5 And 6 Operations

    CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 6.4 8-Bit Timer/Event Counters 5 and 6 Operations 6.4.1 Interval timer operations By setting the 8-bit timer mode control registers 5 and 6 (TMC5 and TMC6) as shown in Figure 6-8, it can be operated as an interval timer.

  • Page 114: Interval Timer Operation Timings

    CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 Figure 6-9. Interval Timer Operation Timings Count Clock TMn Count Value CRn0 TCEn Count start INTTMn Interval Time Remarks 1. Interval time = (N + 1) 2. n = 5, 6 Clear Interrupt Request Acknowledge Interval Time...

  • Page 115: 8-Bit Timer/Event Counters 5 And 6 Interval Times

    CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 Table 6-5. 8-Bit Timer/Event Counters 5 and 6 Interval Times Minimum Interval Time TCLn3 TCLn2 TCLn1 TCLn0 MCS = 1 Setting prohibited (200 ns) (400 ns) (800 ns) (1.6 s) (3.2 s) (6.4 s) (12.8 s) (25.6 s)

  • Page 116: External Event Counter Operation

    CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 6.4.2 External event counter operation The external event counter counts the number of external clock pulses to be input to the TI5/PI00/TO5 and TI6/ P101/TO6 pins with 8-bit timer registers 5 and 6 (TM5 and TM6). TM5 and TM6 are incremented each time the valid edge specified with the timer clock select register 5 and 6 (TCL5 and TCL6) is input.

  • Page 117: Square-Wave Output

    CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 6.4.3 Square-wave output This makes the value set in advance in the 8-bit conveyor register 50, 60 (CR50, CR60) to be the interval. It operates as a square wave output at the desired frequency. The TO5/P100/TI5 or TO6/P101/TI6 pin output status is reversed at intervals of the count value preset to CR50 or CR60 by setting bit 1 (TMC51) and bit 0 (TOE5) of 8-bit timer output control register 5 (TMC5), or bit 1 (TMC61) and bit 0 (TOE6) of 8-bit timer mode control register 6 (TMC6) to 1.

  • Page 118: 8-Bit Timer/Event Counters 5 And 6 Square-Wave Output Ranges

    CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 Table 6-6. 8-Bit Timer/Event Counters 5 and 6 Square-Wave Output Ranges Minimum Pulse Width MCS = 1 MCS = 0 — (200 ns) (200 ns) (400 ns) (400 ns) (800 ns) (800 ns) (1.6 s) (1.6 s) (3.2 s)

  • Page 119: Pwm Output Operations

    CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 6.4.4 PWM output operations Setting the 8-bit timer mode control registers 5 and 6 (TMC5 and TMC6) as shown in Figure 6-13 allows operation as PWM output. Pulses with the duty ratio determined by the values preset in the 8-bit compare registers 50 and 60 (CR50 and CR60) output from the TO5/P100/TI5 or TO6/P101/TI6 pin.

  • Page 120: Pwm Output Operation Timing (Active High Setting)

    CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 Figure 6-14. PWM Output Operation Timing (Active high setting) Count Clock TMn Count Value CRn0 TCEn INTTMn OVFn Inactive Level Remark n = 5, 6 Figure 6-15. PWM Output Operation Timings (CRn0 = 00H, active high setting) Count Clock TMn Count Value CRn0...

  • Page 121: Pwm Output Operation Timings (Crn0 = Ffh, Active High Setting)

    CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 Figure 6-16. PWM Output Operation Timings (CRn0 = FFH, active high setting) Count Clock TMn Count Value CRn0 TCEn INTTMn OVFn Inactive Level Inactive Level Active Level Inactive Level Active Level Remark n = 5, 6...
  • Page 122 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6...

  • Page 123: Cautions On 8-Bit Timer/Event Counters 5 And 6

    CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 6.5 Cautions on 8-Bit Timer/Event Counters 5 and 6 (1) Timer start errors An error with a maximum of one clock may occur concerning the time required for a match signal to be gener- ated after timer start.

  • Page 124: Timing After Compare Register Change During Timer Count Operation

    CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 (3) Operation after compare register change during timer count operation If the values after the 8-bit compare registers 50 and 60 (CR50 and CR60) are changed are smaller than those of 8-bit timer registers 5 and 6 (TM5 and TM6), TM5 and TM6 continue counting, overflow and then restart counting from 0.
  • Page 125 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 [MEMO]...

  • Page 126: Chapter 7 Watchdog Timer

    7.1 Watchdog Timer Functions The watchdog timer has the following functions. • Watchdog timer • Interval timer Caution Select the watchdog timer mode or the interval timer mode with the watchdog timer mode register (WDTM) (The watchdog timer and interval timer cannot be used at the same time). (1) Watchdog timer mode An inadvertent program loop is detected.

  • Page 127: Interval Times

    (2) Interval timer mode Interrupt requests are generated at the preset time intervals. Interval Time Remarks 1. f : Main system clock frequency (f 2. f : Main system clock oscillation frequency 3. MCS : Oscillation mode selection register (OSMS) bit 0 4.

  • Page 128: Watchdog Timer Configuration

    7.2 Watchdog Timer Configuration The watchdog timer consists of the following hardware. Item Control register Prescaler Timer Clock Select Register 2 CHAPTER 7 WATCHDOG TIMER Table 7-3. Watchdog Timer Configuration Configuration Timer clock select register 2 (TCL2) Watchdog timer mode register (WDTM) Figure 7-1.

  • Page 129: Watchdog Timer Control Registers

    7.3 Watchdog Timer Control Registers The following two types of registers are used to control the watchdog timer. • Timer clock select register 2 (TCL2) • Watchdog timer mode register (WDTM) (1) Timer clock select register 2 (TCL2) This register sets the watchdog timer count clock. TCL2 is set with 8-bit memory manipulation instruction.

  • Page 130: Timer Clock Select Register 2 Format

    Figure 7-2. Timer Clock Select Register 2 Format Symbol TCL27 TCL26 TCL25 TCL2 Watchdog Timer Count Clock Selection TCL22 TCL21 TCL20 Buzzer Output Frequency Selection TCL27 TCL26 TCL25 Buzzer output disable Setting prohibited Caution 1. When rewriting TCL2 to other data, stop the timer operation beforehand. 2.

  • Page 131: Watchdog Timer Mode Register Format

    (2) Watchdog timer mode register (WDTM) This register sets the watchdog timer operating mode and enables/disables counting. WDTM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets WDTM to 00H. Figure 7-3. Watchdog Timer Mode Register Format Symbol WDTM4 WDTM3...

  • Page 132: Watchdog Timer Operations

    7.4 Watchdog Timer Operations 7.4.1 Watchdog timer operation When bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1, the watchdog timer is operated to detect any inadvertent program loop. The watchdog timer count clock (inadvertent program loop detection time interval) can be selected with bits 0 to 2 (TCL20 to TCL22) of the timer clock select register 2 (TCL2).

  • Page 133: Interval Timer Operation

    7.4.2 Interval timer operation The watchdog timer operates as an interval timer which generates interrupt requests repeatedly at an interval of the preset count value when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 0. A count clock (interval time) can be selected by the bits 0 to 2 (TCL20 to TCL22) of the timer clock select register 2 (TCL2).

  • Page 134: Chapter 8 Clock Output Control Circuit

    CHAPTER 8 CLOCK OUTPUT CONTROL CIRCUIT 8.1 Clock Output Control Circuit Functions The clock output control circuit is intended for carrier output during remote controlled transmission and clock output for supply to peripheral LSI. Clocks selected with the timer clock select register 0 (TCL0) are output from the PCL/ P35 pin.

  • Page 135: Clock Output Control Circuit Configuration

    CHAPTER 8 CLOCK OUTPUT CONTROL CIRCUIT 8.2 Clock Output Control Circuit Configuration The clock output control circuit consists of the following hardware. Table 8-1. Clock Output Control Circuit Configuration Item Control register Figure 8-2. Clock Output Control Circuit Block Diagram CLOE TCL03 TCL02 TCL01 TCL00 Timer Clock Select Register 0 Configuration...

  • Page 136: Clock Output Function Control Registers

    CHAPTER 8 CLOCK OUTPUT CONTROL CIRCUIT 8.3 Clock Output Function Control Registers The following two types of registers are used to control the clock output function. • Timer clock select register 0 (TCL0) • Port mode register 3 (PM3) (1) Timer clock select register 0 (TCL0) This register sets PCL output clock.

  • Page 137: Port Mode Register 3 Format

    CHAPTER 8 CLOCK OUTPUT CONTROL CIRCUIT (2) Port mode register 3 (PM3) This register set port 3 input/output in 1-bit units. When using the P35/PCL pin for clock output function, set PM35 and output latch of P35 to 0. PM3 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM3 to FFH.

  • Page 138: Chapter 9 Buzzer Output Control Circuit

    CHAPTER 9 BUZZER OUTPUT CONTROL CIRCUIT CHAPTER 9 BUZZER OUTPUT CONTROL CIRCUIT 9.1 Buzzer Output Control Circuit Functions The buzzer output control circuit outputs 1.2 kHz, 2.4 kHz, 4.9 kHz, or 9.8 kHz frequency square waves. The buzzer frequency selected with timer clock select register 2 (TCL2) is output from the BUZ/P36 pin. Follow the procedure below to output the buzzer frequency.

  • Page 139: Buzzer Output Function Control Registers

    CHAPTER 9 BUZZER OUTPUT CONTROL CIRCUIT 9.3 Buzzer Output Function Control Registers The following two types of registers are used to control the buzzer output function. • Timer clock select register 2 (TCL2) • Port mode register 3 (PM3) (1) Timer clock select register 2 (TCL2) This register sets the buzzer output frequency.

  • Page 140: Timer Clock Select Register 2 Format

    CHAPTER 9 BUZZER OUTPUT CONTROL CIRCUIT Figure 9-2. Timer Clock Select Register 2 Format Symbol TCL27 TCL26 TCL25 TCL2 Watchdog Timer Count Clock Selection TCL22 TCL21 TCL20 Buzzer Output Frequency Selection TCL27 TCL26 TCL25 Buzzer output disable Setting prohibited Cautions 1. When rewriting TCL2 to other data, stop the timer operation beforehand. 2.

  • Page 141: Port Mode Register 3 Format

    CHAPTER 9 BUZZER OUTPUT CONTROL CIRCUIT (2) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units. When using the P36/BUZ pin for buzzer output function, set PM36 and output latch of P36 to 0. PM3 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM3 to FFH.

  • Page 142: Chapter 10 A/D Converter

    10.1 A/D Converter Functions The A/D converter converts an analog input into a digital value. It consists of 8 channels (ANI0 to ANI7) with an 8-bit resolution. The conversion method is based on successive approximation and the conversion result is held in the 8-bit A/D conversion result register (ADCR).

  • Page 143: A/D Converter Block Diagram

    Figure 10-1. A/D Converter Block Diagram Internal Bus A/ D Converter Input Select Register ADIS3 ADIS2 ADIS1 ADIS0 ANI0/P10 ANI1/P11 ANI2/P12 Note 1 Note 2 ANI3/P13 ANI4/P14 ANI5/P15 ANI6/P16 ANI7/P17 Edge INTP3/P03 Detector Note 3 ES40, ES41 Trigger Enable TRG FR1 FR0 ADM3 ADM2 ADM1 A/D Converter Mode Register Notes 1.
  • Page 144 (1) Successive approximation register (SAR) This register compares the analog input voltage value to the voltage tap (compare voltage) value applied from the series resistor string and holds the result from the most significant bit (MSB). When held to the least significant bit (LSB) (end of A/D conversion), the contents of the SAR are transferred to the A/D conversion results register.

  • Page 145: A/D Converter Control Registers

    10.3 A/D Converter Control Registers The following three types of registers are used to control the A/D converter. • A/D converter mode register (ADM) • A/D converter input select register (ADIS) • External interrupt mode register 1 (INTM1) (1) A/D converter mode register (ADM) This register sets the analog input channel for A/D conversion, conversion time, conversion start/stop and external trigger.

  • Page 146: A/D Converter Mode Register Format

    Figure 10-2. A/D Converter Mode Register Format Symbol ADM3 ADM3 ADM2 ADM1 Analog Input Channel Selection ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 A/D Conversion Time Selection =5.0 MHz Operation MCS=1 80/f Setting prohibited 40/f Setting prohibited 50/f Setting prohibited 100/f (20.0 s) Other than above...

  • Page 147: A/D Converter Input Select Register Format

    (2) A/D converter input select register (ADIS) This register determines whether the ANI0/P10 to ANI7/P17 pins should be used for analog input channels or ports. Pins other than those selected as analog input can be used as input/output ports. ADIS is set with an 8-bit memory manipulation instruction. RESET input sets ADIS to 00H.

  • Page 148: External Interrupt Mode Register 1 Format

    (3) External interrupt mode register 1 (INTM1) This register sets the valid edge for INTP3. INTM1 is set with an 8-bit memory manipulation instruction. RESET input sets INTM1 to 00H. Figure 10-4. External Interrupt Mode Register 1 Format Symbol INTM1 Caution Set 0 to the bits 2 to 7.

  • Page 149: A/D Converter Operations

    10.4 A/D Converter Operations 10.4.1 Basic operations of A/D converter (1) Set the number of analog input channels with A/D converter input select register (ADIS). (2) From among the analog input channels set with ADIS, select one channel for A/D conversion with A/D converter mode register (ADM).

  • Page 150: A/D Converter Basic Operation

    Sampling Time A/D Converter Sampling Operation Undefined ADCR INTAD A/D conversion operations are performed continuously until bit 7 (CS) of A/D converter mode register (ADM) is reset (0) by software. If a write to the ADM is performed during an A/D conversion operation, the conversion operation is initialized, and if the CS bit is set (1), conversion starts again from the beginning.

  • Page 151: Input Voltage And Conversion Results

    10.4.2 Input voltage and conversion results The relation between the analog input voltage input to the analog input pins (ANI0 to ANI7) and the A/D conversion result (the value stored in A/D conversion result register (ADCR)) is shown by the following expression. ADCR = INT ( 256 + 0.5) (ADCR –...

  • Page 152: A/D Converter Operating Mode

    10.4.3 A/D converter operating mode Using the A/D converter input select register (ADIS) and the A/D converter mode register (ADM), select one channel for the analog input from ANI0 to ANI7 and start A/D conversion. The following two ways are available to start A/D conversion. •...

  • Page 153: A/D Conversion By Software Start

    (2) A/D conversion operation in software start When bit 6 (TRG) and bit 7 (CS) of A/D converter mode register (ADM) are set to 0 and 1, respectively, the A/D conversion starts on the voltage applied to the analog input pins specified with bits 1 to 3 (ADM1 to ADM3) of ADM.

  • Page 154: A/D Converter Cautions

    10.5 A/D Converter Cautions (1) Power consumption in standby mode The A/D converter operates on the main system clock. Therefore, its operation stops in STOP mode. As a current still flows in the AV power dissipation. In Figure 10-9, the power dissipation can be reduced by outputting a low-level signal to the output port in standby mode.

  • Page 155: Analog Input Pin Disposition

    (3) Noise countermeasures In order to maintain 8-bit resolution, attention must be paid to noise on pins AV the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally as shown in Figure 10-10 in order to reduce noise. Reference Voltage Input C=100-1000 pF...
  • Page 156 (6) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the A/D converter mode register (ADM) is changed. Caution is therefore required since, if a change of analog input pin is performed during A/D conversion, the A/D conversion result and ADIF for the pre-change analog input may be set just before the ADM rewrite, and when ADIF is read immediately after the ADM rewrite, ADIF may be set despite the fact that the A/D conversion for the post-change analog input has not ended.
  • Page 157 CHAPTER 10 A/D CONVERTER [MEMO]...

  • Page 158: Chapter 11 Serial Interface Channel 2

    CHAPTER 11 SERIAL INTERFACE CHANNEL 2 11.1 Serial Interface Channel 2 Functions Serial interface channel 2 has the following three modes. • Operation stop mode • Asynchronous serial interface (UART) mode • 3-wire serial I/O mode (1) Operation stop mode This mode is used when serial transfer is not carried out to reduce power consumption.

  • Page 159: Serial Interface Channel 2 Configuration

    11.2 Serial Interface Channel 2 Configuration Serial interface channel 2 consists of the following hardware. Table 11-1. Serial Interface Channel 2 Configuration Item Register Control register CHAPTER 11 SERIAL INTERFACE CHANNEL 2 Configuration Transmit shift register (TXS) Receive shift register (RXS) Receive buffer register (RXB) Serial operating mode register 2 (CSIM2) Asynchronous serial interface mode register (ASIM)

  • Page 160: Serial Interface Channel 2 Block Diagram

    Figure 11-1. Serial Interface Channel 2 Block Diagram Receive Buffer Register (RXB/SIO2) Direction Control Circuit Receive Shift RxD/SI2/ Register (RXS) TxD/SO2/ PM71 Reception Control Circuit PM72 ASCK/ SCK2/P72 Serial Operating Mode Register 2 Note See Figure 11-2 for the baud rate generator configuration. CHAPTER 11 SERIAL INTERFACE CHANNEL 2 Internal Bus Asynchronous...

  • Page 161: Baud Rate Generator Block Diagram

    Figure 11-2. Baud Rate Generator Block Diagram CSIE2 Transmit Clock Receive Clock Start Bit Detection CHAPTER 11 SERIAL INTERFACE CHANNEL 2 5-Bit Counter Match MDL0-MDL3 Decoder Match 5-Bit Counter TPS3 TPS2 TPS1 TPS0 Baud Rate Generator Control Register Start Bit Sampling Clock ASCK/SCK2/P72 Selector...
  • Page 162 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 (1) Transmit shift register (TXS) This register is used to set the transmit data. The data written in TXS is transmitted as serial data. If the data length is specified as 7 bits, bits 0 to 6 of the data written in TXS are transferred as transmit data. Writing data to TXS starts the transmit operation.

  • Page 163: Serial Interface Channel 2 Control Registers

    11.3 Serial Interface Channel 2 Control Registers Serial interface channel 2 is controlled by the following four registers. • Serial Operating Mode Register 2 (CSIM2) • Asynchronous Serial Interface Mode Register (ASIM) • Asynchronous Serial Interface Status Register (ASIS) • Baud Rate Generator Control Register (BRGC) (1) Serial operating mode register 2 (CSIM2) This register is set when serial interface channel 2 is used in the 3-wire serial I/O mode.

  • Page 164: Asynchronous Serial Interface Mode Register Format

    CHAPTER 11 SERIAL INTERFACE CHANNEL 2 (2) Asynchronous serial interface mode register (ASIM) This register is set when serial interface channel 2 is used in the asynchronous serial interface mode. ASIM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIM to 00H.

  • Page 165: Serial Interface Channel 2 Operating Mode Settings

    Table 11-2. Serial Interface Channel 2 Operating Mode Settings (1) Operation Stop Mode ASIM CSIM2 TXE RXE SCK CSIE2 CSIM22 CSCK Other than above (2) 3-wire Serial I/O Mode ASIM CSIM2 TXE RXE SCK CSIE2 CSIM22 CSCK Other than above (3) Asynchronous Serial Interface Mode ASIM CSIM2...

  • Page 166: Asynchronous Serial Interface Status Register Format

    (3) Asynchronous serial interface status register (ASIS) This is a register which displays the type of error when a reception error is generated in the asynchronous serial interface mode. ASIS is read with a 1-bit or 8-bit memory manipulation instruction. In 3-wire serial I/O mode, the contents of the ASIS are undefined.

  • Page 167: Baud Rate Generator Control Register Format (1/2)

    (4) Baud rate generator control register (BRGC) This register sets the serial clock for serial interface channel 2. BRGC is set with an 8-bit memory manipulation instruction. RESET input sets BRGC to 00H. Figure 11-6. Baud Rate Generator Control Register Format (1/2) Symbol BRGC TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0 MDL3 MDL2 MDL1 MDL0...

  • Page 168: Baud Rate Generator Control Register Format (2/2)

    CHAPTER 11 SERIAL INTERFACE CHANNEL 2 Figure 11-6. Baud Rate Generator Control Register Format (2/2) TPS3 TPS2 TPS1 TPS0 Other than above Setting prohibited Caution When a write is performed to BRGC during a communication operation, baud rate generator output is disrupted and communication cannot be performed normally. Therefore, BRGC must not be written to during a communication operation.

  • Page 169: Relation Between Main System Clock And Baud Rate

    CHAPTER 11 SERIAL INTERFACE CHANNEL 2 The baud rate transmit/receive clock generated is either a signal scaled from the main system clock, or a signal scaled from the clock input from the ASCK pin. (a) Generation of baud rate transmit/receive clock by means of main system clock The transmit/receive clocks generated by scaling the main system clock.

  • Page 170: Relation Between Asck Pin Input Frequency And Baud Rate (When Brgc Is Set To 00H)

    CHAPTER 11 SERIAL INTERFACE CHANNEL 2 (b) Generation of baud rate transmit/receive clock by means of external clock from ASCK pin The transmit/receive clock is generated by scaling the clock input from the ASCK pin. The baud rate generated from the clock input from the ASCK pin is obtained with the following expression. ASCK [Baud rate] = (k+16)

  • Page 171: Serial Interface Channel 2 Operation

    11.4 Serial Interface Channel 2 Operation Serial interface channel 2 has the following three modes. • Operation stop mode • Asynchronous serial interface (UART) mode • 3-wire serial I/O mode 11.4.1 Operation stop mode In the operation stop mode, serial transfer is not performed, and therefore power consumption can be reduced. In the operation stop mode, the P70/SI2/RxD, P71/SO2/TxD and P72/SCK2/ASCK pins can be used as normal input/output ports.
  • Page 172 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 (b) Asynchronous serial interface mode register (ASIM) ASIM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIM to 00H. Symbol ASIM Address ISRM SCK FF70H Receive Operation Control Receive operation stopped Receive operation enabled Transmit Operation Control Transmit operation stopped...

  • Page 173: Asynchronous Serial Interface (Uart) Mode

    11.4.2 Asynchronous serial interface (UART) mode In this mode, one byte of data is transmitted/received following the start bit, and full-duplex operation is possible. A dedicated UART baud rate generator is incorporated, allowing communication over a wide range of baud rates. In addition, the baud rate can be defined by scaling the input clock to the ASCK pin.
  • Page 174 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 (b) Asynchronous serial interface mode register (ASIM) ASIM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIM to 00H. Symbol ASIM Note When SCK is set to 1 and the baud rate generator output is selected, the ASCK pin can be used as an input/output port.
  • Page 175 (c) Asynchronous serial interface status register (ASIS) ASIS is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIS to 00H. Symbol ASIS Notes 1. The receive buffer register (RXB) must be read when an overrun error is generated. Overrun errors will continue to be generated until RXB is read.
  • Page 176 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 (d) Baud rate generator control register (BRGC) BRGC is set with an 8-bit memory manipulation instruction. RESET input sets BRGC to 00H. Symbol BRGC TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0 MDL3 MDL2 MDL1 MDL0 Remark : 5-bit counter source clock : Value set in MDL0 to MDL3 (0...
  • Page 177 TPS3 TPS2 TPS1 TPS0 Other than above Caution When a write is performed to BRGC during a communication operation, baud rate generator output is disrupted and communication cannot be performed normally. Therefore, BRGC must not be written to during a communication operation. Remarks 1.

  • Page 178: Relation Between Main System Clock And Baud Rate

    CHAPTER 11 SERIAL INTERFACE CHANNEL 2 The baud rate transmit/receive clock generated is either a signal scaled from the main system clock, or a signal scaled from the clock input from the ASCK pin. (i) Generation of baud rate transmit/receive clock by means of main system clock The transmit/receive clock is generated by scaling the main system clock.

  • Page 179: Relation Between Asck Pin Input Frequency And Baud Rate (When Brgc Is Set To 00H)

    (ii) Generation of baud rate transmit/receive clock by means of external clock from ASCK pin The transmit/receive clock is generated by scaling the clock input from the ASCK pin. The baud rate generated from the clock input from the ASCK pin is obtained with the following expression. [Baud rate] = where, ASCK...

  • Page 180: Asynchronous Serial Interface Transmit/Receive Data Format

    CHAPTER 11 SERIAL INTERFACE CHANNEL 2 (2) Communication operation (a) Data format The transmit/receive data format is as shown in Figure 11-7. Figure 11-7. Asynchronous Serial Interface Transmit/Receive Data Format Start 1 Data frame is configured from the following bits. •...
  • Page 181 (b) Parity types and operation The parity bit is used to detect a bit error in the communication data. Normally, the same kind of parity bit is used on the transmitting side and the receiving side. With even parity and odd parity, a one-bit (odd number) error can be detected.

  • Page 182: Asynchronous Serial Interface Transmission Completion Interrupt Request Timing

    CHAPTER 11 SERIAL INTERFACE CHANNEL 2 (c) Transmission A transmit operation is started by writing transmit data to the transmit shift register (TXS). The start bit, parity bit and stop bit(s) are added automatically. When the transmit operation starts, the data in the transmit shift register (TXS) is shifted out, and when the transmit shift register (TXS) is empty, a transmission completion interrupt request (INTST) is generated.

  • Page 183: Asynchronous Serial Interface Reception Completion Interrupt Request Timing

    (d) Reception When the RXE bit of the asynchronous serial interface mode register (ASIM) is set (1), a receive operation is enabled and sampling of the RxD pin input is performed. RxD pin input sampling is performed using the serial clock specified by ASIM. When the RxD pin input becomes low, the 5-bit counter of the baud rate generator (see Figure 11-2) starts counting, and at the time when the half time determined by specified baud rate has passed, the data sampling start timing signal is output.

  • Page 184: Receive Error Causes

    CHAPTER 11 SERIAL INTERFACE CHANNEL 2 (e) Receive errors Three kinds of errors can occur during a receive operation: a parity error, framing error, or overrun error. When a data reception results error flag is set in the asynchronous serial interface register (ASIS), a reception error interrupt request (INTSER) is generated.
  • Page 185 (3) UART mode cautions (a) In cases where bit 7 (TXE) of the asynchronous serial interface mode register (ASIM) has been cleared and a transmit operation has been terminated during transmission, be sure to set 1 in TXE after setting FFH in the transmit shift register (TXS) before executing the next transmission.

  • Page 186: 3-Wire Serial I/O Mode

    11.4.3 3-wire serial I/O mode The 3-wire serial I/O mode is useful for connection of peripheral I/Os and display controllers, etc., which incorporate a conventional synchronous clocked serial interface, such as the 75X/XL series, 78K series, 17K series, etc. Communication is performed using three lines: the serial clock (SCK2), serial output (SO2), and serial input (SI2). (1) Register setting 3-wire serial I/O mode settings are performed using serial operating mode register 2 (CSIM2), the asynchro- nous serial interface mode register (ASIM), and the baud rate generator control register (BRGC).
  • Page 187 (b) Asynchronous serial interface mode register (ASIM) ASIM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIM to 00H. When the 3-wire serial I/O mode is selected, 00H should be set in ASIM. Symbol ASIM CHAPTER 11 SERIAL INTERFACE CHANNEL 2 Address ISRM SCK...
  • Page 188 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 (c) Baud rate generator control register (BRGC) BRGC is set with an 8-bit memory manipulation instruction. RESET input sets BRGC to 00H. Symbol BRGC TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0 MDL3 MDL2 MDL1 MDL0 Remark : 5-bit counter source clock : Value set in MDL0 to MDL3 (0...
  • Page 189 TPS3 TPS2 TPS1 TPS0 Other than above Caution When a write is performed to BRGC during a communication operation, baud rate generator output is disrupted and communication cannot be performed normally. Therefore, BRGC must not be written to during a communication operation. Remarks 1.
  • Page 190 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 When the internal clock is used as the serial clock in the 3-wire serial I/O mode, set BRGC as described below. BRGC Setting is not required if an external serial clock is used. (i) When the baud rate generator is not used: Select a serial clock frequency with TPS0-TPS3.

  • Page 191: Wire Serial I/O Mode Timing

    CHAPTER 11 SERIAL INTERFACE CHANNEL 2 (2) Communication operation In the 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. Data is transmitted/ received bit by bit in synchronization with the serial clock. Transmit shift register (TXS/SIO2) and receive shift register (RXS) shift operations are performed in synchronization with the fall of the serial clock SCK2.

  • Page 192: Circuit Of Switching In Transfer Bit Order

    CHAPTER 11 SERIAL INTERFACE CHANNEL 2 Figure 11-13. Circuit of Switching in Transfer Bit Order Internal Bus LSB-first MSB-first Transmission Shift Register (TXS/SIO02) SCK2 Start bit switching is realized by switching the bit order for data write to SIO2. The SIO2 shift order remains unchanged.
  • Page 193 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 [MEMO]...

  • Page 194: Chapter 12 Interrupt Function

    12.1 Interrupt Function Types The following three types of interrupt functions are used. (1) Non-maskable interrupt This interrupt is acknowledged unconditionally even in the interrupt disabled status. It does not undergo interrupt priority control and is given top priority over all other interrupt requests. It generates a standby release signal.

  • Page 195: Interrupt Sources And Configuration

    12.2 Interrupt Sources and Configuration There are a total of 13 interrupts, combining non-maskable interrupts, maskable interrupts and software interrupts (see Table 12-1). Note 1 Interrupt Default Type Priority Name Non- — INTWDT maskable Maskable INTWDT INTP1 INTP2 INTP3 INTSER INTSR INTCSI2 INTST...

  • Page 196: Basic Configuration Of Interrupt Function (1/2)

    CHAPTER 12 INTERRUPT FUNCTION Figure 12-1. Basic Configuration of Interrupt Function (1/2) (A) Internal non-maskable interrupt Interrupt Request (B) Internal maskable interrupt Interrupt Request Internal Bus Vector Table Priority Control Address Circuit Generator Internal Bus Priority Control Circuit Standby Release Signal Vector Table Address Generator...

  • Page 197: Basic Configuration Of Interrupt Function (2/2)

    Figure 12-1. Basic Configuration of Interrupt Function (2/2) (C) External maskable interrupt External Interrupt Mode Register (INTM0, INTM1) Interrupt Edge Request Detector (D) Software interrupt Interrupt Request Remark ISP : MK : PR : CHAPTER 12 INTERRUPT FUNCTION Internal Bus Internal Bus Priority Control Circuit...

  • Page 198: Interrupt Function Control Registers

    12.3 Interrupt Function Control Registers The following five types of registers are used to control the interrupt functions. • Interrupt request flag register (IF0L, IF0H, IF1L) • Interrupt mask flag register (MK0L, MK0H, MK1L) • Priority specify flag register (PR0L, PR0H, PR1L) •...

  • Page 199: Interrupt Request Flag Register Format

    (1) Interrupt request flag registers (IF0L, IF0H, IF1L) The interrupt request flag is set to 1 when the corresponding interrupt request is generated or an instruction is executed. It is cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon application of RESET input.

  • Page 200: Interrupt Mask Flag Register Format

    (2) Interrupt mask flag registers (MK0L, MK0H, MK1L) The interrupt mask flag is used to enable/disable the corresponding maskable interrupt service and to set standby clear enable/disable. MK0L, MK0H, and MK1L are set with a 1-bit or 8-bit memory manipulation instruction. If MK0L and MK0H are used as a 16-bit register MK0, use a 16-bit memory manipulation instruction for the setting.

  • Page 201: Priority Specify Flag Register Format

    (3) Priority specify flag registers (PR0L, PR0H, and PR1L) The priority specify flag is used to set the corresponding maskable interrupt priority orders. PR0L, PR0H, and PR1L are set with a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H are used as a 16-bit register PR0, use a 16-bit memory manipulation instruction for the setting.

  • Page 202: External Interrupt Mode Register 0 Format

    (4) External interrupt mode register (INTM0, INTM1) These registers set the valid edge for INTP1 to INTP3. INTM0 and INTM1 are set by 8-bit memory manipulation instructions. RESET input sets these registers to 00H. Figure 12-5. External Interrupt Mode Register 0 Format Symbol INTM0 ES31...

  • Page 203: Program Status Word Configuration

    (5) Program status word (PSW) The program status word is a register to hold the instruction execution result and the current status for interrupt request. The IE flag to set maskable interrupt enable/disable and the ISP flag to control multiple interrupt processing are mapped.

  • Page 204: Interrupt Servicing Operations

    12.4 Interrupt Servicing Operations 12.4.1 Non-maskable interrupt request acknowledge operation A non-maskable interrupt request is unconditionally acknowledged even if in an interrupt request acknowledge disable state. It does not undergo interrupt priority control and has highest priority over all other interrupts. If a non-maskable interrupt request is acknowledged, the contents of program status word (PSW) and program counter (PC), in that order, are saved to the stack, the IE flag and ISP flag are reset (0), and the contents of the vector table are loaded in the PC and branched.

  • Page 205: Flowchart From Non-Maskable Interrupt Request Generation To Acknowledgment

    Figure 12-8. Flowchart from Non-Maskable Interrupt Request Generation to Acknowledgment Figure 12-9. Non-Maskable Interrupt Request Acknowledge Timing CPU Instruction Instruction TMIF4 Interrupt requests which generate within this space are acknowledged with CHAPTER 12 INTERRUPT FUNCTION Start WDTM4=1 (with watchdog timer mode selected)? Overflow in WDT? WDTM3=0...

  • Page 206: Non-Maskable Interrupt Request Acknowledge Operation

    CHAPTER 12 INTERRUPT FUNCTION Figure 12-10. Non-Maskable Interrupt Request Acknowledge Operation If a new non-maskable interrupt request is generated during non-maskable interrupt servicing program execution Main Routine NMI Request NMI Request 1 Instruction Execution If two non-maskable interrupt requests are generated during non-maskable interrupt servicing program execution Main Routine NMI Request...

  • Page 207: Maskable Interrupt Request Acknowledge Operation

    12.4.2 Maskable interrupt request acknowledge operation A maskable interrupt request becomes acknowledgeable when an interrupt request flag is set to 1 and the interrupt mask (MK) flag is cleared to 0. A vectored interrupt request is acknowledged in an interrupt enable state (with IE flag set to 1).

  • Page 208: Interrupt Request Acknowledge Processing Algorithm

    Figure 12-11. Interrupt Request Acknowledge Processing Algorithm Interrupt request reserve Do any of the simultaneously generated requests have a high priority? Interrupt request reserve IE=1? Interrupt request reserve Vectored interrupt servicing : Interrupt request flag MK : Interrupt mask flag PR : Priority specify flag : Flag which controls maskable interrupt request acknowledgment (1 = enable, 0 = disable) : Flag which indicates the priority of the interrupt currently being processed.

  • Page 209: Interrupt Request Acknowledge Timing (Maximum Time)

    Figure 12-12. Interrupt Request Acknowledge Timing (Minimum Time) CPU Processing Instruction PR=1) PR=0) Remark 1 clock : Figure 12-13. Interrupt Request Acknowledge Timing (Maximum Time) CPU Processing Instruction PR=1) PR=0) Remark 1 clock : CHAPTER 12 INTERRUPT FUNCTION Instruction : CPU clock) 25 Clocks Divide Instruction 33 Clocks...

  • Page 210: Software Interrupt Request Acknowledge Operation

    12.4.3 Software interrupt request acknowledge operation A software interrupt request is acknowledged by BRK instruction execution. Software interrupt cannot be disabled. If a software interrupt request is acknowledged, the contents are saved to the stack in the order of first, program status word (PSW), then the program counter (PC), then the IE flag is reset (0) and the contents of the vector tables (003EH, 003FH) are loaded into the PC and branched.

  • Page 211: Interrupt Request Enabled For Multiple Interrupt During Interrupt Servicing

    Table 12-4. Interrupt Request Enabled for Multiple Interrupt during Interrupt Servicing Multiple Interrupt Request Interrupt during processing Non-maskable interrupt Maskable interrupt Software interrupt Remarks 1. D : Multiple interrupt disable ISP and IE are the flags contained in PSW PR is a flag contained in PR0L, PR0H, and PR1L CHAPTER 12 INTERRUPT FUNCTION Maskable Interrupt Request Non-maskable...
  • Page 212 Figure 12-14. Multiple Interrupt Example (1/2) Example 1. Example of when a multiple interrupt is generated twice. Main Processing INTxx (PR=1) Two interrupt requests, INTyy and INTzz, are acknowledged during processing of interrupt INTxx, and a multiple interrupt is generated. Before each interrupt request is acknowledged, the EI instruction is always executed and interrupt request acknowledgment enabled.
  • Page 213 Figure 12-14 Multiple Interrupt Example (2/2) Example 3. Example of when a multiple interrupt is not generated because interrupts are not enabled. Main Processing INTxx (PR=0) 1 Instruction Execution Because interrupts are not enabled (the EI instruction is not executed) during processing of interrupt INTxx , interrupt request INTyy is not acknowledged and a multiple interrupt is not generated.

  • Page 214: Interrupt Request Reserve

    12.4.5 Interrupt request reserve There are some instructions which, though an interrupt request may be generated while they are being executed, will reserve the acknowledgment of the request until after execution of the next instruction. These instructions (interrupt request reserve instructions) are shown below. •...

  • Page 215: Interrupt Request Hold

    The interrupt request reserve timing is shown in Figure 12-15. CPU processing Instruction N Remarks 1. Instruction N: Instruction that holds interrupts requests 2. Instruction M: Instructions other than instruction N 3. The operation of CHAPTER 12 INTERRUPT FUNCTION Figure 12-15. Interrupt Request Hold Instruction M IF (interrupt request) is not affected by Save PSW and PC,...

  • Page 216: Chapter 13 Standby Function

    13.1 Standby Function and Configuration 13.1.1 Standby function The standby function is designed to decrease power consumption of the system. The following two modes are available. (1) HALT mode HALT instruction execution sets the HALT mode. The HALT mode is intended to stop the CPU operation clock. System clock oscillator continues oscillation.

  • Page 217: Standby Function Control Register

    13.1.2 Standby function control register A wait time after the STOP mode is cleared upon interrupt request till the oscillation stabilizes is controlled with the oscillation stabilization time select register (OSTS). OSTS is set with an 8-bit memory manipulation instruction. RESET input sets OSTS to 04H.

  • Page 218: Standby Function Operations

    13.2 Standby Function Operations 13.2.1 HALT mode (1) HALT mode set and operating status The HALT mode is set by executing the HALT instruction. The operating status in the HALT mode is described below. Item Clock generator Port 8-bit timer/event counter 5, 6 Watchdog timer A/D converter Serial interface...

  • Page 219: Halt Mode Clear Upon Interrupt Generation

    (2) HALT mode clear The HALT mode can be cleared with the following three types of sources. (a) Clear upon unmasked interrupt request An unmasked interrupt request is used to clear the HALT mode. If interrupt acknowledge is enabled, vectored interrupt service is carried out. If disabled, the next address instruction is executed. Figure 13-2.

  • Page 220: Operation After Halt Mode Release

    CHAPTER 13 STANDBY FUNCTION (c) Clear upon RESET input As is the case with normal reset operation, a program is executed after branch to the reset vector address. Figure 13-3. HALT Mode Release by RESET Input HALT Instruction RESET Signal Operating Mode HALT Mode...

  • Page 221: Stop Mode

    13.2.2 STOP mode (1) STOP mode set and operating status The STOP mode is set by executing the STOP instruction. Cautions 1. When the STOP mode is set, the X2 pin is internally connected to V to minimize the leakage current at the crystal oscillator. Thus, do not use the STOP mode in a system where an external clock is used for the main system clock.

  • Page 222: Stop Mode Release By Interrupt Generation

    (2) STOP mode release The STOP mode can be cleared with the following two types of sources. (a) Release by unmasked interrupt request An unmasked interrupt request is used to release the STOP mode. If interrupt acknowledge is enabled after the lapse of oscillation stabilization time, vectored interrupt service is carried out. If interrupt acknowledge is disabled, the next address instruction is executed.

  • Page 223: Operation After Stop Mode Release

    (b) Release by RESET input The STOP mode is cleared and after the lapse of oscillation stabilization time, reset operation is carried out. Figure 13-5. Release by STOP Mode RESET Input STOP Instruction RESET Signal Operating Mode Oscillation Clock Remarks 1. f : main system clock oscillation frequency 2.

  • Page 224: Chapter 14 Reset Function

    14.1 Reset Function The following two operations are available to generate the reset signal. (1) External reset input with RESET pin (2) Internal reset by watchdog timer overrun time detection External reset and internal reset have no functional differences. In both cases, program execution starts at the address at 0000H and 0001H by RESET input.

  • Page 225: Timing Of Reset Input By Reset Input

    Figure 14-2. Timing of Reset Input by RESET Input Normal Operation RESET Internal Reset Signal Port Pin Figure 14-3. Timing of Reset due to Watchdog Timer Overflow Normal Operation Watchdog Timer Overflow Internal Reset Signal Port Pin Figure 14-4. Timing of Reset Input in STOP Mode by RESET Input STOP Instruction Execution Normal Operation RESET...
  • Page 226 Table 14-1. Hardware Status after Reset (1/2) Note1 Program counter (PC) Stack pointer (SP) Program status word (PSW) Port (Output latch) Port mode register (PM0, PM1, PM3, PM5, PM7, PM10) Pull-up resistor option register (PUOH, PUOL) Processor clock control register (PCC) Oscillation mode selection register (OSMS) Memory size switching register (IMS) Oscillation stabilization time select register (OSTS)
  • Page 227 Table 14-1. Hardware Status after Reset (2/2) Interrupt Notes 1. During reset input or oscillation stabilization time wait, only the PC contents among the hardware statuses become undefined. All other hardware statuses remains unchanged after reset. 2. The post-reset status is held in the standby mode. 3.

  • Page 228: Chapter 15 Pd78P083

    The PD78P083 is a single-chip microcontroller with an on-chip one-time PROM or with an on-chip EPROM which has program write, erasure and rewrite capability. Differences between the PD78P083 and mask ROM versions are shown in Table 15-1. Table 15-1. Differences between the PD78P083 and Mask ROM Versions Parameter Internal ROM type Internal ROM capacity...

  • Page 229: Memory Size Switching Register

    15.1 Memory Size Switching Register It is possible to specify the internal memory of the PD78P083 by means of the memory size switching register (IMS). By setting the IMS, memory mapping can be made to match the memory mapping of the PD78081 and 78082, which have different internal memory.

  • Page 230: Prom Programming

    15.2 PROM Programming The PD78P083 incorporate a 24-Kbyte PROM as program memory, respectively. To write a program into the PD78P083 PROM, make the device enter the PROM programming mode by setting the levels of the V and RESET pins as specified. For the connection of unused pins, see paragraph (2) “PROM programming mode”...
  • Page 231 (3) Standby mode Setting CE to H sets the standby mode. In this mode, data output becomes high impedance irrespective of the status of OE. (4) Page data latch mode Setting CE to H, PGM to H, and OE to L at the start of the page write mode sets the page data latch mode. In this mode, 1-page 4-byte data is latched in the internal address/data latch circuit.

  • Page 232: Prom Write Procedure

    15.2.2 PROM write procedure Address = Address + 1 Pass CHAPTER 15 PD78P083 Figure 15-2. Page Program Mode Flowchart Start Address = G = 6.5 V, V = 12.5 V X = 0 Latch Address = Address + 1 Latch Address = Address + 1 Latch Address = Address + 1...

  • Page 233: Page Program Mode Timing

    Page Data Latch A2-A14 A0, A1 D0-D7 +1.5 CHAPTER 15 PD78P083 Figure 15-3. Page Program Mode Timing Page Program Data Input Program Verify Data Output...

  • Page 234: Byte Program Mode Flowchart

    Figure 15-4. Byte Program Mode Flowchart Address = Address + 1 Pass CHAPTER 15 PD78P083 Start Address = G = 6.5 V, V = 12.5 V X = 0 X = X + 1 0.1-ms program pulse Fail Verify Pass Address = N? = 4.5 to 5.5 V, V Fail...

  • Page 235: Byte Program Mode Timing

    A0-A14 D0-D7 +1.5 Cautions 1. Be sure to apply V 2. V must not exceed +13.5 V including overshoot voltage. 3. Disconnecting/inserting the device from/to the on-board socket while +12.5 V is being applied to the V pin may have an adverse affect on device reliability. CHAPTER 15 PD78P083 Figure 15-5.

  • Page 236: Prom Reading Procedure

    CHAPTER 15 PD78P083 15.2.3 PROM reading procedure PROM contents can be read onto the external data bus (D0 to D7) using the following procedure. (1) Fix the RESET pin low, and supply +5 V to the V pin. Unused pins are handled as shown in paragraph, (2) “PROM programming mode”...

  • Page 237: Erasure Procedure ( Pd78P083Du Only)

    15.3 Erasure Procedure ( PD78P083DU Only) With the PD78P083DU, it is possible to erase ( or set all contents to FFH) the data contents written in the program memory, and rewrite the memory. The data can be erased by exposing the window to light with a wavelength of approximately 400 nm or shorter. Typically, data is erased by 254-nm ultraviolet light rays.

  • Page 238: Chapter 16 Instruction Set

    CHAPTER 16 INSTRUCTION SET CHAPTER 16 INSTRUCTION SET This chapter describes each instruction set of the PD78083 subseries as list table. For details of its operation and operation code, refer to the separate document “78K/0 series USER’S MANUAL—Instruction (IEU-1372).”...

  • Page 239: Legends Used In Operation List

    16.1 Legends Used in Operation List 16.1.1 Operand identifiers and description methods Operands are described in “Operand” column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for detail). When there are two or more description methods, select one of them.

  • Page 240: Description Of "Operation" Column

    16.1.2 Description of “operation” column : A register; 8-bit accumulator : X register : B register : C register : D register : E register : H register : L register : AX register pair; 16-bit accumulator : BC register pair : DE register pair : HL register pair : Program counter...

  • Page 241: Operation List

    16.2 Operation List Instruction Mnemonic Operands Group r, #byte saddr, #byte sfr, #byte A, r r, A A, saddr saddr, A A, sfr sfr, A A, !addr16 !addr16, A PSW, #byte A, PSW PSW, A A, [DE] 8-bit data [DE], A transfer A, [HL] [HL], A...
  • Page 242 Instruction Mnemonic Operands Group rp, #word saddrp, #word sfrp, #word AX, saddrp saddrp, AX 16-bit MOVW AX, sfrp data sfrp, AX transfer AX, rp rp, AX AX, !addr16 !addr16, AX XCHW AX, rp A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL]...
  • Page 243 Instruction Mnemonic Operands Group A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C] A, #byte saddr, #byte A, r r, A A, saddr 8-bit SUBC operation...
  • Page 244 Instruction Mnemonic Operands Group A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C] A, #byte saddr, #byte A, r r, A A, saddr 8-bit operation A, !addr16...
  • Page 245 Instruction Mnemonic Operands Group ADDW AX, #word 16-bit SUBW AX, #word operation CMPW AX, #word MULU Multiply/ divide DIVUW saddr Increment/ decrement saddr INCW DECW A, 1 A, 1 RORC A, 1 ROLC A, 1 Rotate ROR4 [HL] ROL4 [HL] ADJBA adjust ADJBS...
  • Page 246 Instruction Mnemonic Operands Group CY, saddr.bit CY, sfr.bit AND1 CY, A.bit CY, PSW.bit CY, [HL].bit CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit CY, [HL].bit CY, saddr.bit CY, sfr.bit XOR1 CY, A.bit manipu- CY, PSW. bit late CY, [HL].bit saddr.bit sfr.bit SET1 A.bit...
  • Page 247 Instruction Mnemonic Operands Group CALL !addr16 CALLF !addr11 CALLT [addr5] Call/return RETI RETB PUSH Stack manipu- late SP, #word MOVW SP, AX AX, SP !addr16 Uncondi- tional $addr16 branch $addr16 $addr16 Conditional branch $addr16 $addr16 Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access 2.
  • Page 248 Instruction Mnemonic Operands Group saddr.bit, $addr16 sfr.bit, $addr16 A.bit, $addr16 PSW.bit, $addr16 [HL].bit, $addr16 saddr.bit, $addr16 sfr.bit, $addr16 A.bit, $addr16 PSW.bit, $addr16 [HL].bit, $addr16 Condi- saddr.bit, $addr16 tional branch sfr.bit, $addr16 BTCLR A.bit, $addr16 PSW.bit, $addr16 [HL].bit, $addr16 B, $addr16 DBNZ C, $addr16 saddr.

  • Page 249: Instructions Listed By Addressing Type

    CHAPTER 16 INSTRUCTION SET 16.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ...
  • Page 250 Second Operand #byte First Operand ADDC SUBC MOV MOV ADDC SUBC B, C MOV MOV saddr MOV MOV ADDC SUBC !addr16 MOV MOV [DE] [HL] [HL + byte] [HL + B] [HL + C] Note Except r = A CHAPTER 16 INSTRUCTION SET Note saddr !addr16 PSW MOV MOV MOV MOV MOV MOV MOV MOV...
  • Page 251 (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Second Operand #word First Operand ADDW SUBW CMPW MOVW MOVW sfrp MOVW MOVW saddrp MOVW MOVW !addr16 MOVW MOVW MOVW Note Only when rp = BC, DE, HL (3) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR Second Operand...
  • Page 252 (4) Call/instructions/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ Second Operand First Operand Basic instruction Compound instruction (5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP CHAPTER 16 INSTRUCTION SET !addr16 !addr11 CALL...
  • Page 253 CHAPTER 16 INSTRUCTION SET [MEMO]...

  • Page 254: Appendix A Development Tools

    APPENDIX A DEVELOPMENT TOOLS APPENDIX A DEVELOPMENT TOOLS The following development tools are available for the development of systems which employ the PD78083 subseries. Figure A-1 shows the configuration of the development tools.
  • Page 255 Figure A-1. Development Tool Configuration Embedded software • Real-time OS, OS • Fuzzy inference development support system PROM writing environments PROM programmer Programmer adapter PROM containing version APPENDIX A DEVELOPMENT TOOLS PROM programmer control software Language processing software • Assembler package •...

  • Page 256: Language Processing Software

    APPENDIX A DEVELOPMENT TOOLS RA78K/0 CC78K/0 DF78083 CC78K0-L Host Machine PC-9800 Series MS-DOS (Ver. 3.30 to 6.2 IBM PC/AT and their Refer to A.4 compatible machines HP9000 series 300™ HP-UX™ (rel. 7.05B) HP9000 series 700™ HP-UX (rel. 9.01) SPARCstation™ SunOS™ (rel. 4.1.1) EWS-4800 series (RISC) EWS-UX/V (rel.

  • Page 257: Prom Programming Tools

    PG1500 Host Machine PC-9800 Series MS-DOS (Ver. 3.30 to 6.2 IBM PC/AT and their Refer to A.4 compatible machines The task swap function is not available with this software through the function is provided in MS-DOS version 5.0 or later.

  • Page 258: Debugging Tools

    Interface adapter machine for the IE-78000-R-A. IE-70000-PC-IF-B This is an adapter necessary when using IBM PC/AT as a host machine for the IE-78000-R-A. Interface adapter IE-78000-R-SV3 This is an adapter and cable necessary when using EWS as a host machine for the IE-78000-R- Interface adapter As Ethernet™, 10Base-5 is supported.

  • Page 259: Software (1/3)

    APPENDIX A DEVELOPMENT TOOLS SM78K0 Host Machine PC-9800 Series MS-DOS (Ver. 3.30 to 6.2 Windows (Ver. 3.0 to 3.1) IBM PC/AT and their Refer to A.4 compatible machines (Windows in Japanese) IBM PC/AT and their compatible machines (Windows in English) Medium 3.5-inch 2HD...

  • Page 260: Software (2/3)

    APPENDIX A DEVELOPMENT TOOLS ID78K0 Host Machine PC-9800 Series MS-DOS (Ver. 3.30 to 6.2 Windows (Ver. 3.1) IBM PC/AT and their Refer to A.4 compatible machines (Windows in Japanese) IBM PC/AT and their compatible machines (Windows in English) HP9000 series 700 HP-UX (rel.

  • Page 261: Software (3/3)

    DF78083 Host Machine PC-9800 Series MS-DOS (Ver. 3.30 to 6.2 IBM PC/AT and their Refer to A.4 compatible machines (Windows in Japanese) The task swap function is not available with this software through the function is provided in MS-DOS version 5.0 or later.

  • Page 262: Os For Ibm Pc

    A.4 OS for IBM PC As the OS for IBM PC, the following is supported. To run SM78K0, ID78K0, or FE9200 (refer to B.2 Fuzzy Inference Development Support System), Windows (Ver. 3.0 to Ver. 3.1) is necessary. Note Caution The task swap function is not available with this software through the function is provided in MS-DOS version 5.0 or later.

  • Page 263: System-Upgrade Method From Other In-Circuit Emulators To 78K/0 Series In-Circuit Emulator

    A.5 System-Upgrade Method from Other In-Circuit Emulators to 78K/0 Series In-Circuit Emulator If you already have an in-circuit emulator for the 78K series or the 75X/XL series, you can use that in-circuit emulator as the equivalent of the 78K/0 series in-circuit emulator IE-78000-R or IE-78000-R-A by replacing the internal break board with the IE-78000-R-BK.
  • Page 264 Drawing and Footprint for Conversion Socket (EV-9200G-44) Figure A-2. EV-9200G-44 Drawing (For Reference Only) Based on EV-9200G-44 (1) Package drawing (in mm) No.1 pin index APPENDIX A DEVELOPMENT TOOLS EV-9200G-44 ITEM EV-9200G-44-G0E MILLIMETERS INCHES 15.0 0.591 10.3 0.406 10.3 0.406 15.0 0.591 4-C 3.0...
  • Page 265 Figure A-3. EV-9200G-44 Footprint (For Reference Only) Based on EV-9200G-44 (2) Pad drawing (in mm) ITEM MILLIMETERS 15.7 11.0 0.8 ± 0.02 10=8.0 ± 0.05 0.8 ± 0.02 10=8.0 ± 0.05 11.0 15.7 5.00 ± 0.08 5.00 ± 0.08 0.5 ± 0.02 1.57 ±...

  • Page 266: Appendix B Embedded Software

    APPENDIX B EMBEDDED SOFTWARE APPENDIX B EMBEDDED SOFTWARE This section describes the embedded software which are provided for the PD78083 subseries to allow users to develop and maintain the application program for these subseries.

  • Page 267: Real-Time Os

    Can be purchased only when object for mass production has been purchased. Host Machine PC-9800 Series MS-DOS (Ver. 3.30 to 6.2 IBM PC/AT and their Refer to A.4 compatible machines HP9000 series 300 HP-UX (rel. 7.05B) HP9000 series 700 HP-UX (rel. 9.01) SPARCstation SunOS (rel.

  • Page 268: Fuzzy Inference Development Support System

    FE9000 (PC-9800 series) FE9200 (IBM PC/AT and their compatible machines) FT9080 (PC-9800 series) FT9085 (IBM PC/AT and their compatible machines) FI78K0 (PC-9800 series, IBM PC/AT and their compatible machines) FD78K0 (PC-9800 series, IBM PC/AT and their compatible machines) Host Machine PC-9800 Series MS-DOS (Ver.
  • Page 269 APPENDIX B EMBEDDED SOFTWARE [MEMO]...

  • Page 270: Appendix C Register Index

    C.1 Register Index 8-bit timer mode control register (TMC5) ... 87 8-bit timer register 5 (TM5) ... 79, 84 8-bit timer register 6 (TM6) ... 79, 84 ADCR: A/D conversion result register ... 121 ADIS: A/D converter input select register ... 124 ADM: A/D converter mode register ...
  • Page 271 Port0 ... 17, 55 Port1 ... 17, 57 Port3 ... 18, 58 Port5 ... 18, 59 Port7 ... 19, 60 P10: Port10 ... 19, 62 PCC: Processor clock control register ... 71, 76, 77 PM0: Port mode register 0 ... 63 PM1: Port mode register 1 ...

  • Page 272: Appendix D Revision History

    Major revisions by edition and revised chapters are shown below. Edition Major revisions from previous version The following products have been already developed PD78081CU- , 78081GB- 78082GB- -3B4, 78P083CU, 78P083DU, 78P083GB-3B4 The following products have been added PD78081GB- -3BS-MTX, 78082GB- 780P083GB-3BS-MTX, 78081GB(A)- 78P083CU(A), 78P083GB(A)-3B4, 78P083GB(A)-3BS-MTX, 78081GB(A2)-...
  • Page 273 The following Development Tools have been added: IE-78000-R-A, IE-70000-98-IF-B, IE-70000-98-N-IF, IE-70000-PC-IF-B, IE-78000-R-SV3, SM78K0, ID78K0 A.4 OS for IBM PC has been added. Table A-2. System-Up Method from Other In-Circuit Emulator to IE-78000-R-A has been added. B.1 Real-time OS has been added.
  • Page 274 Facsimile From: Name Company Tel. Address North America NEC Electronics Inc. Corporate Communications Dept. Fax: 1-800-729-9288 1-408-588-6130 Europe NEC Electronics (Europe) GmbH Technical Documentation Dept. Fax: +49-211-6503-274 South America NEC do Brasil S.A. Fax: +55-11-889-1689 I would like to report the following error/make the following suggestion: Document title: Document number: If possible, please fax the referenced page or drawing.

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