NEC PD78081(A) User Manual page 18

Fig. No.
6-10 8-Bit Timer Mode Control Register Setting for External Event Counter Operation .............
6-11 External Event Counter Operation Timings (with Rising Edge Specification) ....................
6-12 8-Bit Timer Mode Control Register Settings for Square-Wave Output Operation ..............
6-13 8-Bit Timer Mode Control Register Settings for PWM Output Operation ...........................
6-14 PWM Output Operation Timing (Active high setting) ..........................................................
6-15 PWM Output Operation Timings (CRn0 = 00H, active high setting) ...................................
6-16 PWM Output Operation Timings (CRn0 = FFH, active high setting) ..................................
6-17 PWM Output Operation Timings (CRn0 changing, active high setting) ..............................
6-18 8-Bit Timer Registers 5 and 6 Start Timing .........................................................................
6-19 External Event Counter Operation Timing ..........................................................................
6-20 Timing after Compare Register Change during Timer Count Operation ............................
7-1 Watchdog Timer Block Diagram .........................................................................................
7-2 Timer Clock Select Register 2 Format ................................................................................
7-3 Watchdog Timer Mode Register Format .............................................................................
8-1 Remote Controlled Output Application Example ................................................................
8-2 Clock Output Control Circuit Block Diagram .......................................................................
8-3 Timer Clock Select Register 0 Format ................................................................................
8-4 Port Mode Register 3 Format .............................................................................................
9-1 Buzzer Output Control Circuit Block Diagram ....................................................................
9-2 Timer Clock Select Register 2 Format ................................................................................
9-3 Port Mode Register 3 Format .............................................................................................
10-1 A/D Converter Block Diagram ............................................................................................
10-2 A/D Converter Mode Register Format ................................................................................
10-3 A/D Converter Input Select Register Format ......................................................................
10-4 External Interrupt Mode Register 1 Format ........................................................................
10-5 A/D Converter Basic Operation ..........................................................................................
10-6 Relations between Analog Input Voltage and A/D Conversion Result ................................
10-7 A/D Conversion by Hardware Start ....................................................................................
10-8 A/D Conversion by Software Start ......................................................................................
10-9 Example of Method of Reducing Current Dissipation in Standby Mode .............................
10-10 Analog Input Pin Disposition ..............................................................................................
10-11 A/D Conversion End Interrupt Request Generation ...........................................................
10-12 Handling of AVDD Pin .........................................................................................................
11-1 Serial Interface Channel 2 Block Diagram .........................................................................
11-2 Baud Rate Generator Block Diagram .................................................................................
11-3 Serial Operating Mode Register 2 Format ..........................................................................
11-4 Asynchronous Serial Interface Mode Register Format .......................................................
11-5 Asynchronous Serial Interface Status Register Format .....................................................
11-6 Baud Rate Generator Control Register Format (1/2) .........................................................
FIGURE (2/4)
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