System Clock Control Register 2 (Sycc2) - Fujitsu 8FX Hardware Manual

CHAPTER 3 CLOCK CONTROLLER
3.3 Registers
3.3.5

System Clock Control Register 2 (SYCC2)

The system clock control register 2 (SYCC2) indicates the respective
stabilization conditions of main clock oscillation, subclock oscillation, main CR
clock oscillation and sub-CR clock oscillation, and controls main clock
oscillation, subclock oscillation, main CR clock oscillation and sub-CR clock
oscillation.
■ Register Configuration
bit 7
Field SRDY
Attribute R
Initial value X
■ Register Functions
[bit7] SRDY: Subclock oscillation stabilization bit
This bit indicates whether the subclock oscillation has become stable.
This bit is read-only. Writing a value to this bit has no effect on operation.
bit7
Reading "0"
Reading "1"
[bit6] MRDY: Main clock oscillation stabilization bit
This bit indicates whether the main clock oscillation has become stable.
This bit is read-only. Writing a value to this bit has no effect on operation.
bit6
Reading "0"
Reading "1"
[bit5] SCRDY: Sub-CR clock oscillation stabilization bit
This bit indicates whether the sub-CR clock oscillation has become stable.
This bit is read-only. Writing a value to this bit has no effect on operation.
bit5
Reading "0"
Reading "1"
[bit4] MCRDY: Main CR clock oscillation stabilization bit
This bit indicates whether the main CR clock oscillation has become stable.
This bit is read-only. Writing a value to this bit has no effect on operation.
bit4
Reading "0"
Reading "1"
34
6 5
MRDY SCRDY
R R
X X
Indicates that the clock controller is in the subclock oscillation stabilization wait state or that the
subclock oscillation has stopped.
Indicates that the subclock oscillation wait time is over.
Indicates that the clock controller is in the main clock oscillation stabilization wait state or that the
main clock oscillation has stopped.
Indicates that the main clock oscillation wait time is over.
Indicates that the clock controller is in the sub-CR clock oscillation stabilization wait state or that
the sub-CR clock oscillation has stopped.
Indicates that the sub-CR clock oscillation wait time is over.
Indicates that the clock controller is in the main CR clock oscillation stabilization wait state or
that the main CR clock oscillation has stopped.
Indicates that the main CR clock oscillation wait time is over.
FUJITSU SEMICONDUCTOR LIMITED
4 3
MCRDY SOSCE
R R/W
X 0
Details
Details
Details
Details
MB95630H Series
2 1
MOSCE SCRE
R/W R/W
0 1
MN702-00009-2v0-E
0
MCRE
R/W
1