Fujitsu 8FX Hardware Manual page 344

CHAPTER 18 8/16-BIT PPG
18.7 Registers
[bit2:0] CKS1[2:0]: Operating clock select bits
These bits select the operating clock for 8-bit downcounter of the PPG timer n1.
The operating clock is generated from the prescaler. For details, see "3.9 Operation of Prescaler".
In 16-bit PPG mode, the settings of these bits have no effect on the operation.
bit2:0
Writing "000"
Writing "001"
Writing "010"
Writing "011"
Writing "100"
Writing "101"
Writing "110"
Writing "111"
Note: In subclock mode or sub-CR clock mode, since the time-base timer stops operating, setting CKS1[2:0]
to "0b110" or "0b111" is prohibited.
322
(MCLK: machine clock, F
F : main CR clock, F
CRH
1 MCLK
MCLK/2
MCLK/4
MCLK/8
MCLK/16
MCLK/32
7 6
F /2 or F /2 or F
CH CRH MCRPLL
8 7
F /2 or F /2 or F
CH CRH MCRPLL
FUJITSU SEMICONDUCTOR LIMITED
Details
: main clock,
CH
: main CR PLL clock)
MCRPLL
6
/2
7
/2
MB95630H Series
MN702-00009-2v0-E