Configuration - Fujitsu 8FX Hardware Manual

MB95630H Series
15.2

Configuration

The 8/10-bit A/D converter consists of the following blocks:
• Clock selector (input clock selector for starting A/D conversion)
• Analog channel selector
• Sample-and-hold circuit
• Control circuit
• 8/10-bit A/D converter data register (upper/lower) (ADDH/ADDL)
• 8/10-bit A/D converter control register 1 (ADC1)
• 8/10-bit A/D converter control register 2 (ADC2)
The number of analog input pins and that of analog channels of the 8/10-bit A/D converter vary
among products. For details, refer to the device data sheet.
In this chapter, "n" in a pin name represents the analog input pin number. For details of pin
names of a product, refer to the device data sheet.
■ Block Diagram of 8/10-bit A/D Converter
Figure 15.2-1 is the block diagram of the 8/10-bit A/D converter.
Figure 15.2-1 Block Diagram of 8/10-bit A/D Converter
8/16-bit
composite timer
output pin (TO00)
ANn
● Clock selector
This selects the A/D conversion clock with continuous activation having been enabled
(ADC2:EXT = 1).
MN702-00009-2v0-E
8/10-bit A/D converter control register 2 (ADC2)
AD8 TIM1
Startup
signal
selector
Analog Sample-
channel
and-hold
selector
circuit
8/10-bit A/D converter data register(upper/lower)
ANS3 ANS2
8/10-bit A/D converter control register 1 (ADC1)
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 15 8/10-BIT A/D CONVERTER
TIM0 ADCK ADIE EXT
Control circuit
(ADDH/ADDL)
ANS1 ANS0 ADI ADMV
IRQ
15.2 Configuration
CKDIV1 CKDIV0
Reserved AD
265