Fujitsu 8FX Hardware Manual page 541

MB95630H Series
[bit2] GACKE: General call address acknowledge enable bit
This bit controls the general call address acknowledge.
Writing "0" to this bit disables general call address acknowledge output.
With this bit set to "1", in master mode or slave mode, when a general call address acknowledge (0x00) is
received, a general call address acknowledge is output.
bit2
Writing "0"
Writing "1"
[bit1] INTE: Transfer completion interrupt enable bit
This bit enables or disables the transfer completion interrupt.
When this bit and the IBCR1n:INT bit are both set to "1", a transfer completion interrupt request is
generated.
bit1
Writing "0"
Writing "1"
[bit0] INT: Transfer completion interrupt request flag bit
This bit detects the transfer completion.
When this bit and the INTE bit are both set to "1", a transfer completion interrupt request is generated.
If one of the following four conditions is satisfied, upon completion of transferring 1-byte address or data
(the setting of the INTS bit determines whether the 1-byte address or data includes an acknowledge.), this bit
is set to "1".
• In bus master mode
• The device is addressed as slave.
2
• The I C bus interface has received a general call address.
2
• The I C bus interface has detected an arbitration lost.
• Arbitration lost detected
If one of the following two conditions is satisfied, this bit is set to "0".
• "0" is written to this bit.
• In master mode, a repeated START condition (IBCR1n:SCC = 1) or a STOP condition (IBCR1n:MSS = 0) is
generated.
Writing "1" to this bit has no effect on operation.
When read by the read-modify-write (RMW) type of instruction, this bit always returns "1".
Writing "0" to clear this bit (its value becomes "0") releases the SCLn line, and the transmission of the next
byte of data is then enabled.
bit0
Reading "0"
Reading "1"
Writing "0"
Writing "1"
Notes:
• In the case of writing "1" to the SCC bit while this bit is "0", the setting of the SCC bit is given priority, and
a START condition is generated.
• In the case of writing "0" to the MSS bit while this bit is "0", the setting of the MSS bit is given priority, and
a STOP condition is generated.
• During data reception, with the IBCR0n:INTS bit already set to "1", this bit becomes "1" after 1-byte data
(not including an acknowledge) transfer is completed. If the INTS bit is set to "0", this bit becomes "1" after
the transmission/reception of 1-byte data/address (including an acknowledge) is completed.
MN702-00009-2v0-E
Disables the general call address acknowledge.
Enables the general call address acknowledge.
Disables the transfer completion interrupt.
Enables the transfer completion interrupt.
Indicates that data transfer has not been completed.
Indicates that1-byte data (including an acknowledge) transfer has been completed.
Clears this bit.
Has no effect on operation.
FUJITSU SEMICONDUCTOR LIMITED
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CHAPTER 24 I
Details
Details
Details
C BUS INTERFACE
24.7 Registers
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